MicroControllers.

Make your own rudimentary version using less than 50 chips!

MicroControllers (uC's) are greatly simplified versions of microprocessors. They are mainly intended for sensor data gathering, control, or other applications which do not justify a fully- fledged microprocesor. The memory space is in the 64K- 16M region, and 32- bit versions are availiable. The performance can be more than 15 MIPS at a clock speed of 50 MHz, at a cost of a few dollars. Some devices include a serial or parallel port, and a power- down mode may exist for use in battery operated equipment.

Availiable commands include:
The common ground for the addressing modes supported seems to include:

Key: IP: Instruction pointer, DR : (Temporary) data register, ALU/ S: Arithmetic and Logic unit, shifter. SR: Status Register, AR: Address Register, IR: Instruction register, RF: Register File, I: Indices, SP: Stack pointer, A: Accumulator. The control section (which inludes the instruction step counter) connects to all modules, but this is not shown explicitly. All modules, save the program counter, connect to the data bus (not shown for clarity.) The bidirectional data bus is at least 8 bits wide, and the unidirectional address bus from the controller is at least 16 bits wide. The control bus includes the Reset, Interrupt Request and Clock signal to the uC and the Read/ Write' signal from the uC. All buses which do not have an arrow indicator are bidirectional. There are tristate buffers after the IP, AR and SP blocks (not shown), only one of which is active at any time, to avoid address bus contention. An adder (also not shown) combines the AR and index contents if an index displacement mode has been selected. Another adder adds the AR low byte to the PC for relative addressing.

Suppose you tried to make your own rudimentary microcontroller on a 10''x 10'' double- sided board, using individual chips, (why do that?), how low can the IC count go? Would you believe, less than 50! (Mainly small- scale integration, but also some registers, tristate buffers, adders, counters, multiplexers and decoders.) However, all of the niceties of programming would have to go, so microcontroller manufacturers will not worry about this one!

The idea is certainly not new, in fact it goes back to the late 40's, (at least), as in valve circuits every electronic switch in the design must justify its presence. There is also the RISC architecture, officialy availiable since the beginning of the 70's (at least), though not promoted at the time, but this relies on a small command set as well as a large number of registers (16 or 32) and encourages data transfer/ operations between registers, rather than between registers and memory.

Considerable simplification to figure 8 (and the specs mentioned above!) will be necessary before our goal of under 50 chips can materialise: Several programming acrobatics will be required: You would have to contend with a single accumulator. You can eliminate the stack pointer and subsequent tristate buffer, and still have subroutines and interrupts provided you are prepared to manually handle your own (software) stack. Before each branching instruction is executed the hardware must store the contents of the instruction pointer to latches, whose contents you must be able to save in memory, using two different commands (one for the high order byte and one for the low order value.) For interrupts, you must have commands to load from and store the flags to memory.

But the most dramatic reduction in circuit size inevitably stems from accepting a single addressing mode:direct (and absolute for branching instructions.) This has several consequences, none of which is good:In particular, it implies you must use self- modifying code in order to access a block of memory, and the code must be copied to RAM before it can run. You will probably throw up your hands in indignation when you find out that even conditional branching instructions use absolute, rather than relative, addressing: This results in those oft- used instructions occupying 33% more memory space and execution time- maybe it does not matter too much, as the ensuing higher clock speed of the simplified circuit affects all instructions, and partially compensates for that delay. It also implies that programs cannot be relocated in memory without being compiled again. This saves the adder after the address register and related buffer, but, more importantly, handling all instructions in a uniform manner does incur a substantial reduction in circuit size.

The most interesting section, is the control section: This defines which modules get connected to the inputs and outputs of each unit, and at which time. Hence this section drives the output enable and latch inputs of all registers, certain multiplexers in the flags section, and the instruction pointer/ address register multiplexer. It even advances the instruction pointer during each cycle of the fetch phase and conditionally asserts the Read/ write' signal during the execution phase. For such a simple design, hard wiring (combinational logic) is perfectly feasible (and faster) than ROM or microcode implementations. For an 8- bit, 64 K main memory controller, the fetch cycle consists of reading 3 bytes ( a command byte followed by a low and a high address byte) and the execution phase reads (or writes) a further byte from the (direct) address just fetched. The performance is 1 MIPS for every 4 MHz of clock signal. Clock tactics certainly deserve some thought, since a single phase signal is inadequate: Data bits must be latched before the outputs supplying them revert to the high- impedance state; it is no good trying to assess the outputs of a counter before they have settled to a stable state, either.

Speed considerations: You have to be realistic about the performance of a uController made on a board from individual chips, as compared to an integrated design having on- chip cache memory! Small improvements can be made by opting for the negative and zero flags not to be affected by loading registers from memory. However, once the logic family for implementation has been selected, speed is mainly a matter of optimizing the mark- to- space ratio of the clock, and the availiability of a separate clock for the execution phase. You may want to consider the following structure for the command byte:

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