Disadvantages: The image must be still for over 5 seconds, as only a single column of pixels is sampled during each frame. The main software loop runs at the TV line frequency, so an assembler routine is necessary: Almost all high- level languages are not fast enough to acquire and store in excess of 12, 000 samples per second.
The skeleton video digitizer block diagram is in figure 5. The crystal oscillator may be at the TV color frequency, or its multiples. The simple counter will have a minimum of 8 bits, while the programmable counter block will need to be made of more than one ICs in cascade. The programmable counter data inputs (D's) are supplied by the corresponding outputs (Q's) from the plain counter. The Load' signal to the programmable counter is from the mixed sync splitter block. The carry- out pulse triggers the pulse lengthener. The pulse lengthener provides both the control signal to the sample- and- hold, and the SOC' (start- of- conversion) signal to the analog- to- digital converter.The ADC output bits, end- of- conversion (EOC') and mixed sync outputs are led to the computer input port.
Software Description:
The simplicity of the arrangement can be quite deceiptive: It certainly doesn't imply the results are not worthwhile! The reproduction of a 320x512 monochrome screen of 40x32 characters was rendered essentially fault free.