Simplified Simulation Of Analog Electronic Circuits.

The admittance (inverse impedence) matrix of a circuit is best illustrated by an example: Figure I is a simple resistive network. To avoid complication, in this particular example, the nodes are arbitrarily numbered and node 0 is left floating (unconnected.) However, this in general will not be the case. Because charge is neither created nor consumed inside a node, the total current into any node is zero. Nevertheless, it is still useful to write down an expression for them. If the currents (rather than the voltages) are the dependent variables, and assuming linearity:

i1 = (v1-v2)y12 + (v1-v3)y13

i2 = (v2-v1)y21 + (v2-v3)y23

i3 = (v3-v1)y31 + (v3-v2)y32

or, rearranging, i = yv

Now eliminate v3 from all higher equations by the substitution v3 = ( v1y31 + v2y32 ) / (y31 + y32 ). (If more nodes had been present, the additional voltages would have been eliminated iteratively.) Hence, the circuit has been reduced to a two-port network, figure II. If nodes 0, 1 and 2 are always the input, output and earth nodes respectively, it can be shown that:

i0 = y00v0 + y01v1

i1 = y10v0 + y11v1

where ys is the source admittance, yL is the load admittance and Dy = y00y11 - y10y01

The admittance matrix of any linear circuit can be formed by inspection:

The matrix for a transistor is given below. For low frequency work, yre and yoe are usually ignored. yfe is Ie (mA) / (25 mV) approximately, so if (for example) Ie =1 mA, yfe is 1 / (25 Ohms), while yie is yfe / hfe ; therefore if, in addition, hfe = 300 yie = 1 / (300.25 Ohms) = 1 / (7500 Ohms). However, a good design should not depend on the exact value of hfe.

s being yie + yfe + yre + yoe

Notes:

1. In signal terms, all power supply connections are commoned. (This is not to say that the admittance matrix method cannot be used to obtain the DC bias - the quiescent point- of a circuit. However, the transistor YFE is now IE (mA) / 650 milliVolts approximately - for silicon bipolar transistors. Starting from a guess value, it will require a few iterations before the actual transistor current values are obtained.)
2. Oscillators can be evaluated by breaking the loop. The group delay d ( phase ) / dw will require a second calculation very close to the frequency of interest.
3. The steady- state time response to a non- sinusoidal signal can be determined by splitting it to its Fourier components and adding the corresponding responses.
4. Most circuits will contain some inductance or capacitance, so some of the y parameters, gains and two-port impedences will be compex numbers (frequency- variable.) A procedure to reduce that matrix follows (for the nodes numbered 0 to n% inclusive; yr is the real part of the matrix, yi the imaginary, y = yr +j yi .) Sparse matrix techniques could be used to enhance processing and storage.

                   FOR x% = n% TO 3 STEP -1:

                    a=yr(x%,x%)^2 +yi(x%,x%)^2:

                    FOR p% = 0 TO x%-1:

                     FOR q%=0 TO x%-1:

                      b=yr(p%,x%)*yr(x%,q%)-yi(p%,x%)*yi(x%,q%):

                      c=yr(x%,q%)*yi(p%,x%)+yr(p%,x%)*yi(x%,q%):

                      yr(p%,q%) = yr(p%,q%)-(b*yr(x%,x%)+c*yi(x%,x%))/a:

                      yi(p%,q%)=yi(p%,q%)-(c*yr(x%,x%)-b*yi(x%,x%))/a:

                     NEXT q%, p%, x%

Reference: Wireless World magazine (British) Volume 86, February issue, p.39

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