100Base-T Ethernet Repeater Project

Purpose: To design and build a 100Base-T Ethernet Repeater based on the repeater core described in Kevin Skahill's book "VHDL for Programmable Logic"

Project Requirements:

• familiarization with repeater requirements and repeater core requirements
• familiarization with existing VHDL code
• code hierarchical Verilog modules
• research alternate chips
• target new chips using Cypress Semiconductor (Place and Route) software
• test using simulation software and test vectors
• design circuit to include physical layer, transceiver, magnetics and sockets
• design printed circuit board
• assemble and test 

Block Diagram:

Repeater Requirements:

• meet IEEE 802.3u specifications
• detect activity and receive ethernet frames on active ports
• restore shape, amplitude and timing prior to retransmission
• forward the ethernet frame to all active ports
• detect and signal a collision throughout a network
• partition bad segments

Repeater Core Logic Requirements:

• Interface:
  • interface to Physical Layer using Media Independent Interface
  • carrier sense input
  • receive clock input
  • receive data valid input
  • receive data (0-3) input
  • transmit clock output
  • transmit enable output
  • transmit data (0-3) output
  • link integrity
• Protocol:
  • upon carrier sense from any port, receive and buffer data
  • regenerate the preamble and transmit to all active ports
  • generate JAM signal after a collision
  • generate IDLE signal during inactivity
  • generate BAD signal after an error
  • detect jabbering and disable jabbering port
  • enable a disabled port (after sufficient time without carrier sense from that port)