ispEXPERT Compiler Release 7.0.15, Nov  4 1998 14:24:11
 

Design Parameters
-----------------

IGNORE_FIXED_PIN:               OFF
MAX_GLB_IN:                     16
MAX_GLB_OUT:                    4
OS_VERSION:                     Windows 98
PARAM_FILE:                     ispxpert
RESERVE_PIN_FILE:               nocane2.rsp
STRATEGY:                       AREA
TIMING_ANALYZER:                OFF
 

Design Specification
--------------------

Design:                         nocane2
Part:                           ispLSI2064-80LJ84
 

ISP:                            ON
PULL:                           OFF
SECURITY:                       ON
 

Number of Critical Pins:        1
Number of Free Pins:            0
Number of Locked Pins:          57
Number of Reserved Pins:        0
 

Input Pins

    Pin Name                Pin Attribute

        A0                      LOCK 53
        A1                      LOCK 16
        A10                     LOCK 26
        A11                     LOCK 48
        A12                     LOCK 34
        A13                     LOCK 78
        A14                     LOCK 54
        A15                     LOCK 74
        A2                      LOCK 75
        A3                      LOCK 69
        A4                      LOCK 5
        A5                      LOCK 51
        A6                      LOCK 37
        A7                      LOCK 4
        A8                      LOCK 18
        A9                      LOCK 27
        AVMA                    LOCK 38
        BA                      LOCK 28
        BLK0                    LOCK 50, PULLUP
        BLK1                    LOCK 45, PULLUP
        CAS                     LOCK 70
        CPU0                    LOCK 33
        CPU1                    LOCK 41
        CPURST                  LOCK 57
        D0                      LOCK 15
        D1                      LOCK 60
        E                       LOCK 31
        FAST                    LOCK 82, PULLUP
        HSYNC                   LOCK 32
        INPUT20NS               LOCK 17
        MHZ28                   LOCK 83
        Q                       LOCK 56
        RAS                     LOCK 14
        RW                      LOCK 49
        SERINTHI                LOCK 30
        VSYNC                   LOCK 59
 

Output Pins

    Pin Name                Pin Attribute

        DELAY20NS               LOCK 68
        EOUT                    LOCK 71, PULLUP
        FF60_3                  LOCK 6, SLOWSLEW
        FF64_7                  LOCK 13, SLOWSLEW
        FF68_B                  LOCK 12, SLOWSLEW
        FF6C_F                  LOCK 7, SLOWSLEW
        FFAXWR                  LOCK 55, SLOWSLEW
        GREEN_LED               LOCK 29
        INTSERLO                LOCK 77
        IORW                    LOCK 36, SLOWSLEW
        NEWCAS                  LOCK 8, SLOWSLEW
        NEWRAS                  LOCK 3, SLOWSLEW
        QOUT                    LOCK 81, PULLUP
        RAMADRS0                LOCK 73, SLOWSLEW
        RAMADRS1                LOCK 52, SLOWSLEW
        RAMADRS2                LOCK 47, SLOWSLEW
        RAMADRS3                LOCK 46, SLOWSLEW
        RED_LED                 LOCK 76
        RESHIGH                 LOCK 11, SLOWSLEW
        SERIAL                  LOCK 72, SLOWSLEW
        SIMM_A9                 CRIT, LOCK 9
 

Protected Gates

    Instance Name           Gate Name

        N_2                     PLA
        N_45                    PLA
        N_70                    PLA
        N_77                    PLA
 

Preserved Nets

    Net Name

        N_73
 

Pre-Route Design Statistics
---------------------------

Number of Macrocells:           46
Number of GLBs:                 14
Number of I/Os:                 57
Number of Nets:                 82

Number of Free Inputs:          0
Number of Free Outputs:         0
Number of Free Three-States:    0
Number of Free Bidi's:          0

Number of Locked Input IOCs:    36
Number of Locked DIs:           0
Number of Locked Outputs:       20
Number of Locked Three-States:  1
Number of Locked Bidi's:        0

Number of CRIT Outputs:         1
Number of Global OEs:           0
Number of External Clocks:      0
 

GLB Utilization (Out of 16): 87%
I/O Utilization (Out of 64): 89%
Net Utilization (Out of 128): 64%
 

Nets with Fanout of  1:         48
Nets with Fanout of  2:         8
Nets with Fanout of  3:         7
Nets with Fanout of  4:         15
Nets with Fanout of  5:         2
Nets with Fanout of  6:         1
Nets with Fanout of  8:         1

Average Fanout per Net:         2.06
 

GLBs with  3 Input(s):          3
GLBs with  6 Input(s):          1
GLBs with  9 Input(s):          1
GLBs with 10 Input(s):          1
GLBs with 13 Input(s):          2
GLBs with 14 Input(s):          3
GLBs with 15 Input(s):          2
GLBs with 16 Input(s):          1

Average Inputs per GLB:         10.57
 

GLBs with  1 Output(s):         2
GLBs with  2 Output(s):         1
GLBs with  3 Output(s):         2
GLBs with  4 Output(s):         9

Average Outputs per GLB:        3.29
 

Output Enable Nets:             1

    Net Name                Net Fanout

    _BUF_1095                   1
 

Number of GLB Registers:        14
Number of IOC Registers:        0
 

Post-Route Design Implementation
--------------------------------

Number of Macrocells:  46
Number of GLBs:   15
Number of IOCs:   57
Number of DIs:   0
Number of GLB Levels:  3
 

GLB glb00, A3

    13 Input(s)
        (A0.O, A0X, I8), (A1.O, A1X, I9), (A4.O, A4X, I2), (A5.O,
        A5X, I13), (A6.O, A6X, I0), (A7.O, A7X, I1), (BLK0.O,
        BLK0X, I5), (E.O, EX, I14), (glb11.O3, GREEN_AR, I7), (Q.O,
        QX, I11), (RW.O, RWX, I4), (glb07.O2, _AND_850, I6), (glb04.O3,
        _AND_874_part1, I3)
    4 Output(s)
        (_OR_875, O0), (_OR_863, O1), (_BUF_1106, O2), (GREEN, O3)
    7 Product Term(s)

    Output _OR_875

        5 Input(s)
            QX, A7X, _AND_874_part1, EX, A6X
        3 Fanout(s)
            glb02.I12, glb01_part1.I8, glb04.I3
        2 Product Term(s)
        2 GLB Level(s)

        _OR_875 = (A7X & EX & !A6X & _AND_874_part1
            # A7X & QX & !A6X & _AND_874_part1)

    Output _OR_863

        5 Input(s)
            BLK0X, A5X, A7X, A4X, A6X
        2 Fanout(s)
            glb03.I6, glb08.I2
        2 Product Term(s)
        1 GLB Level(s)

        _OR_863 = (A4X & A5X & A6X & BLK0X & !A7X
            # A5X & A6X & !A7X & !A4X & !BLK0X)

    Output _BUF_1106

        1 Input(s)
            RWX
        1 Fanout(s)
            IORW.IR
        1 Product Term(s)
        1 GLB Level(s)

        _BUF_1106 = RWX

    Output GREEN

        10 Input(s)
            _AND_850, A0X, GREEN_AR, A5X, QX, A7X, RWX, A4X, A1X, A6X
        2 Fanout(s)
            glb05.I4, GREEN_LED.IR
        0 Product Term(s)
        3 GLB Level(s)

        GREEN.D = VCC
        !GREEN.C = A0X & A4X & A6X & A7X & QX & !A1X & !A5X & !RWX
            & _AND_850
        GREEN.R = GREEN_AR
 

GLB glb01_part1, A5

    4 Input(s)
        (E.O, EX, I5), (Q.O, QX, I0), (RW.O, RWX, I4), (glb00.O0,
        _OR_875, I8)
    1 Output(s)
        (_AND_971, O2)
    1 Product Term(s)

    Output _AND_971

        4 Input(s)
            _OR_875, QX, RWX, EX
        1 Fanout(s)
            FFAXWR.IR
        1 Product Term(s)
        3 GLB Level(s)

        _AND_971 = EX & QX & !RWX & _OR_875
 

GLB glb01_part2, A0

    12 Input(s)
        (A0.O, A0X, I3), (A1.O, A1X, I9), (A3.O, A3X, I1), (A4.O,
        A4X, I2), (A5.O, A5X, I6), (A6.O, A6X, I0), (A7.O, A7X, I5),
        (CPURST.O, CPURSTX, I8), (D0.O, D0X, I12), (Q.O, QX, I11),
        (RW.O, RWX, I15), (glb02.O0, _AND_857, I4)
    1 Output(s)
        (N_68, O0)
    3 Product Term(s)

    Output N_68

        12 Input(s)
            A3X, A0X, CPURSTX, A5X, _AND_857, D0X, QX, A7X, RWX, A4X,
            A1X, A6X
        1 Fanout(s)
            glb02.I4
        1 Product Term(s)
        2 GLB Level(s)

        N_68.D = D0X
        !N_68.C = A0X & A4X & A7X & QX & !A1X & !A5X & !RWX & !A3X & !A6X
            & _AND_857
        N_68.R = !CPURSTX
 

GLB glb02, A4

    14 Input(s)
        (A1.O, A1X, I9), (A10.O, A10X, I0), (A11.O, A11X, I3), (A12.O,
        A12X, I8), (A13.O, A13X, I10), (A14.O, A14X, I2), (A15.O,
        A15X, I6), (A2.O, A2X, I7), (A3.O, A3X, I1), (A8.O, A8X, I11),
        (A9.O, A9X, I5), (E.O, EX, I14), (glb01_part2.O0, N_68, I4),
        (glb00.O0, _OR_875, I12)
    4 Output(s)
        (_AND_857, O0), (RAMADRS3_PIN, O1), (RAMADRS2_PIN, O2),
        (RAMADRS1_PIN, O3)
    7 Product Term(s)

    Output _AND_857

        10 Input(s)
            A13X, A8X, A10X, A2X, A15X, A12X, A14X, A9X, A11X, EX
        1 Fanout(s)
            glb01_part2.I4
        1 Product Term(s)
        1 GLB Level(s)

        _AND_857 = A10X & A11X & A12X & A13X & A14X & A15X & A8X & A9X
            & EX & !A2X

    Output RAMADRS3_PIN

        3 Input(s)
            A3X, N_68, _OR_875
        1 Fanout(s)
            RAMADRS3.IR
        2 Product Term(s)
        3 GLB Level(s)

        RAMADRS3_PIN = (A3X & _OR_875
            # N_68 & !_OR_875)

    Output RAMADRS2_PIN

        3 Input(s)
            A2X, A15X, _OR_875
        1 Fanout(s)
            RAMADRS2.IR
        2 Product Term(s)
        3 GLB Level(s)

        RAMADRS2_PIN = (A2X & _OR_875
            # A15X & !_OR_875)

    Output RAMADRS1_PIN

        3 Input(s)
            _OR_875, A14X, A1X
        1 Fanout(s)
            RAMADRS1.IR
        2 Product Term(s)
        3 GLB Level(s)

        RAMADRS1_PIN = (A1X & _OR_875
            # A14X & !_OR_875)
 

GLB glb03, B5

    15 Input(s)
        (A6.O, A6X, I15), (A7.O, A7X, I14), (CPU0.O, CPU0X, I8),
        (CPU1.O, CPU1X, I0), (CPURST.O, CPURSTX, I7), (INPUT20NS.O,
        INPUT20NSX, I5), (glb06.O2, N_169, I9), (glb03.O3, N_262, I17),
        (glb12.O2, N_262_C, I1), (glb11.O2, N_55, I2), (glb11.O1,
        N_59, I10), (Q.O, QX, I4), (glb07.O3, _AND_846, I12),
        (glb00.O1, _OR_863, I6), (glb04.O2, _AND_874_part2, I13)
    4 Output(s)
        (_OR_972, O2), (_BUF_1103, O0), (_AND_970, O1), (N_262, O3)
    10 Product Term(s)

    Output _OR_972

        9 Input(s)
            CPU1X, N_55, INPUT20NSX, QX, A7X, CPU0X, _AND_874_part2,
            N_59, A6X
        1 Fanout(s)
            SIMM_A9.ID
        5 Product Term(s)
        2 GLB Level(s)

        _OR_972 = (INPUT20NSX & QX & !CPU0X
            # QX & !CPU1X & !INPUT20NSX
            # INPUT20NSX & !QX & !N_55
            # !QX & !N_59 & !INPUT20NSX
            # A6X & A7X & QX & _AND_874_part2)

    Output _BUF_1103

        1 Input(s)
            CPURSTX
        1 Fanout(s)
            RESHIGH.IR
        1 Product Term(s)
        1 GLB Level(s)

        _BUF_1103 = CPURSTX

    Output _AND_970

        2 Input(s)
            _AND_846, _OR_863
        1 Fanout(s)
            FF68_B.IR
        1 Product Term(s)
        2 GLB Level(s)

        _AND_970 = _AND_846 & _OR_863

    Output N_262

        3 Input(s)
            N_262_C, N_169, N_262
        3 Fanout(s)
            glb10.I7, glb03.I17, glb13.I8
        1 Product Term(s)
        3 GLB Level(s)

        N_262.D = !N_262
        N_262.C = N_262_C
        N_262.R = N_169
 

GLB glb04, B0

    16 Input(s)
        (A0.O, A0X, I12), (A10.O, A10X, I15), (A11.O, A11X, I8),
        (A12.O, A12X, I7), (A13.O, A13X, I5), (A14.O, A14X, I6),
        (A15.O, A15X, I9), (A4.O, A4X, I13), (A5.O, A5X, I2), (A6.O,
        A6X, I4), (A7.O, A7X, I14), (A8.O, A8X, I0), (A9.O, A9X, I10),
        (BLK1.O, BLK1X, I11), (E.O, EX, I1), (glb00.O0, _OR_875, I3)
    4 Output(s)
        (_OR_881, O0), (_AND_874_part2, O2), (RAMADRS0_PIN, O1),
        (_AND_874_part1, O3)
    6 Product Term(s)

    Output _OR_881

        14 Input(s)
            A13X, A8X, A10X, A5X, A15X, A12X, BLK1X, A7X, A4X, A14X, A9X,
            A11X, EX, A6X
        1 Fanout(s)
            SERIAL.IR
        2 Product Term(s)
        1 GLB Level(s)

        _OR_881 = (A10X & A11X & A12X & A13X & A14X & A15X & A4X & A5X
            & A8X & A9X & BLK1X & EX & !A7X & !A6X
            # A10X & A11X & A12X & A13X & A14X & A15X & A4X & A8X & A9X
            & EX & !A5X & !A7X & !A6X & !BLK1X)

    Output _AND_874_part2

        10 Input(s)
            A13X, A8X, A10X, A5X, A15X, A12X, A4X, A14X, A9X, A11X
        1 Fanout(s)
            glb03.I13
        1 Product Term(s)
        1 GLB Level(s)

        _AND_874_part2 = A10X & A11X & A12X & A13X & A14X & A15X & A5X
            & A8X & A9X & !A4X

    Output RAMADRS0_PIN

        3 Input(s)
            A13X, A0X, _OR_875
        1 Fanout(s)
            RAMADRS0.IR
        2 Product Term(s)
        3 GLB Level(s)

        RAMADRS0_PIN = (A0X & _OR_875
            # A13X & !_OR_875)

    Output _AND_874_part1

        10 Input(s)
            A13X, A8X, A10X, A5X, A15X, A12X, A4X, A14X, A9X, A11X
        1 Fanout(s)
            glb00.I3
        1 Product Term(s)
        1 GLB Level(s)

        _AND_874_part1 = A10X & A11X & A12X & A13X & A14X & A15X & A5X
            & A8X & A9X & !A4X
 

GLB glb05, B2

    9 Input(s)
        (E.O, EX, I10), (FAST.O, FASTX, I5), (glb00.O3, GREEN, I4),
        (glb13.O3, N_257, I0), (glb13.O2, N_258, I1), (glb13.O1,
        N_259, I6), (glb05.O2, N_86, I16), (Q.O, QX, I15), (glb13.O0,
        WAVES, I7)
    4 Output(s)
        (_AND_974, O0), (QOUT_PIN, O1), (N_86, O2), (EOUT_PIN, O3)
    13 Product Term(s)

    Output _AND_974

        2 Input(s)
            N_86, GREEN
        1 Fanout(s)
            RED_LED.IR
        1 Product Term(s)
        1 GLB Level(s)

        _AND_974 = GREEN & N_86

    Output QOUT_PIN

        7 Input(s)
            N_258, N_257, N_86, GREEN, QX, WAVES, N_259
        1 Fanout(s)
            QOUT.IR
        5 Product Term(s)
        1 GLB Level(s)

        QOUT_PIN = (QX & !N_86
            # !GREEN & QX
            # QX & !WAVES & !N_258 & !N_259
            # GREEN & N_257 & N_86 & !WAVES & !N_258
            # GREEN & N_258 & N_259 & N_86 & !WAVES & !N_257)

    Output N_86

        2 Input(s)
            FASTX, QX
        1 Fanout(s)
            glb05.I16
        1 Product Term(s)
        1 GLB Level(s)

        N_86.D = FASTX
        N_86.C = QX

    Output EOUT_PIN

        7 Input(s)
            N_258, N_257, N_86, GREEN, WAVES, N_259, EX
        1 Fanout(s)
            EOUT.IR
        5 Product Term(s)
        1 GLB Level(s)

        EOUT_PIN = (EX & !N_86
            # EX & !GREEN
            # EX & !WAVES & !N_258
            # GREEN & N_257 & N_86 & !WAVES & !N_259
            # GREEN & N_259 & N_86 & !WAVES & !N_258)
 

GLB glb06, B1

    3 Input(s)
        (glb09.O0, N_264, I7), (RAS.O, RASX, I15), (glb12.O0,
        _OR_973, I3)
    3 Output(s)
        (_GND_1158, O1), (_BUF_1105, O0), (N_169, O2)
    3 Product Term(s)

    Output _GND_1158

        0 Input(s)
        1 Fanout(s)
            INTSERLO.IR
        0 Product Term(s)
        0 GLB Level(s)

        _GND_1158 = GND

    Output _BUF_1105

        1 Input(s)
            RASX
        1 Fanout(s)
            DELAY20NS.IR
        1 Product Term(s)
        1 GLB Level(s)

        _BUF_1105 = RASX

    Output N_169

        2 Input(s)
            _OR_973, N_264
        4 Fanout(s)
            glb10.I6, glb09.I9, glb03.I9, glb13.I9
        0 Product Term(s)
        3 GLB Level(s)

        N_169.D = VCC
        !N_169.C = N_264
        N_169.R = !_OR_973
 

GLB glb07, B4

    13 Input(s)
        (A10.O, A10X, I15), (A11.O, A11X, I12), (A12.O, A12X, I7),
        (A13.O, A13X, I5), (A14.O, A14X, I13), (A15.O, A15X, I9),
        (A2.O, A2X, I8), (A3.O, A3X, I14), (A8.O, A8X, I0), (A9.O,
        A9X, I10), (E.O, EX, I1), (glb12.O1, N_78_QB, I6), (RAS.O,
        RASX, I4)
    4 Output(s)
        (_AND_854, O1), (_AND_850, O2), (_AND_846, O3),
        (NEWRAS_PIN, O0)
    4 Product Term(s)

    Output _AND_854

        11 Input(s)
            A3X, A13X, A8X, A10X, A2X, A15X, A12X, A14X, A9X, A11X, EX
        1 Fanout(s)
            glb11.I5
        1 Product Term(s)
        1 GLB Level(s)

        _AND_854 = A10X & A11X & A12X & A13X & A14X & A15X & A3X & A8X
            & A9X & EX & !A2X

    Output _AND_850

        11 Input(s)
            A3X, A13X, A8X, A10X, A2X, A15X, A12X, A14X, A9X, A11X, EX
        1 Fanout(s)
            glb00.I6
        1 Product Term(s)
        1 GLB Level(s)

        _AND_850 = (A10X & A11X & A12X & A13X & A14X & A15X & A3X & A8X
            & A9X & EX & !A2X)

    Output _AND_846

        11 Input(s)
            A3X, A13X, A8X, A10X, A2X, A15X, A12X, A14X, A9X, A11X, EX
        2 Fanout(s)
            glb11.I7, glb03.I12
        1 Product Term(s)
        1 GLB Level(s)

        _AND_846 = (A10X & A11X & A12X & A13X & A14X & A15X & A3X & A8X
            & A9X & EX & !A2X)

    Output NEWRAS_PIN

        3 Input(s)
            RASX, N_78_QB, EX
        1 Fanout(s)
            NEWRAS.IR
        2 Product Term(s)
        1 GLB Level(s)

        NEWRAS_PIN = (RASX
            # EX & N_78_QB)
 

GLB glb08, B6

    15 Input(s)
        (A10.O, A10X, I15), (A11.O, A11X, I12), (A12.O, A12X, I7),
        (A13.O, A13X, I5), (A14.O, A14X, I13), (A15.O, A15X, I9),
        (A2.O, A2X, I8), (A3.O, A3X, I14), (A8.O, A8X, I0), (A9.O,
        A9X, I10), (E.O, EX, I1), (glb11.O0, N_73, I11), (glb12.O1,
        N_78_QB, I6), (RAS.O, RASX, I4), (glb00.O1, _OR_863, I2)
    4 Output(s)
        (_AND_872, O0), (_AND_868, O2), (_AND_865, O3),
        (NEWCAS_PIN, O1)
    5 Product Term(s)

    Output _AND_872

        12 Input(s)
            A3X, A13X, A8X, A10X, A2X, A15X, A12X, _OR_863, A14X, A9X,
            A11X, EX
        1 Fanout(s)
            FF6C_F.IR
        1 Product Term(s)
        2 GLB Level(s)

        _AND_872 = A10X & A11X & A12X & A13X & A14X & A15X & A2X & A3X
            & A8X & A9X & EX & _OR_863

    Output _AND_868

        12 Input(s)
            A3X, A13X, A8X, A10X, A2X, A15X, A12X, _OR_863, A14X, A9X,
            A11X, EX
        1 Fanout(s)
            FF64_7.IR
        1 Product Term(s)
        2 GLB Level(s)

        _AND_868 = A10X & A11X & A12X & A13X & A14X & A15X & A2X & A8X
            & A9X & EX & !A3X & _OR_863

    Output _AND_865

        12 Input(s)
            A3X, A13X, A8X, A10X, A2X, A15X, A12X, _OR_863, A14X, A9X,
            A11X, EX
        1 Fanout(s)
            FF60_3.IR
        1 Product Term(s)
        2 GLB Level(s)

        _AND_865 = A10X & A11X & A12X & A13X & A14X & A15X & A8X & A9X
            & EX & !A2X & !A3X & _OR_863

    Output NEWCAS_PIN

        3 Input(s)
            N_73, RASX, N_78_QB
        1 Fanout(s)
            NEWCAS.IR
        2 Product Term(s)
        2 GLB Level(s)

        NEWCAS_PIN = (N_78_QB & RASX
            # N_73 & !N_78_QB)
 

GLB glb09, B3

    3 Input(s)
        (glb06.O2, N_169, I9), (glb10.O0, N_263, I12), (glb09.O0,
        N_264, I16)
    1 Output(s)
        (N_264, O0)
    3 Product Term(s)

    Output N_264

        3 Input(s)
            N_264, N_169, N_263
        3 Fanout(s)
            glb06.I7, glb09.I16, glb13.I7
        1 Product Term(s)
        1 GLB Level(s)

        N_264.D = !N_264
        !N_264.C = N_263
        N_264.R = N_169
 

GLB glb10, A2

    3 Input(s)
        (glb06.O2, N_169, I6), (glb03.O3, N_262, I7), (glb10.O0,
        N_263, I16)
    1 Output(s)
        (N_263, O0)
    3 Product Term(s)

    Output N_263

        3 Input(s)
            N_169, N_263, N_262
        3 Fanout(s)
            glb10.I16, glb09.I12, glb13.I12
        1 Product Term(s)
        1 GLB Level(s)

        N_263.D = !N_263
        !N_263.C = N_262
        N_263.R = N_169
 

GLB glb11, A1

    14 Input(s)
        (A0.O, A0X, I3), (A1.O, A1X, I9), (A4.O, A4X, I2), (A5.O,
        A5X, I13), (A6.O, A6X, I0), (A7.O, A7X, I1), (CAS.O,
        CASX, I6), (CPURST.O, CPURSTX, I8), (D0.O, D0X, I12), (D1.O,
        D1X, I15), (Q.O, QX, I11), (RW.O, RWX, I4), (glb07.O3,
        _AND_846, I7), (glb07.O1, _AND_854, I5)
    4 Output(s)
        (N_73, O0), (N_59, O1), (N_55, O2), (GREEN_AR, O3)
    7 Product Term(s)

    Output N_73

        1 Input(s)
            CASX
        1 Fanout(s)
            glb08.I11
        1 Product Term(s)
        1 GLB Level(s)

        N_73 = CASX

    Output N_59

        11 Input(s)
            D1X, A0X, CPURSTX, A5X, QX, A7X, RWX, A4X, _AND_854, A1X,
            A6X
        1 Fanout(s)
            glb03.I10
        1 Product Term(s)
        2 GLB Level(s)

        N_59.D = D1X
        !N_59.C = A0X & A1X & A4X & A7X & QX & !A5X & !RWX & !A6X
            & _AND_854
        N_59.R = !CPURSTX

    Output N_55

        11 Input(s)
            A0X, CPURSTX, A5X, D0X, QX, A7X, RWX, A4X, _AND_854, A1X,
            A6X
        1 Fanout(s)
            glb03.I2
        1 Product Term(s)
        2 GLB Level(s)

        N_55.D = D0X
        !N_55.C = A0X & A1X & A4X & A7X & QX & !A5X & !RWX & !A6X
            & _AND_854
        N_55.R = !CPURSTX

    Output GREEN_AR

        10 Input(s)
            A0X, _AND_846, CPURSTX, A5X, QX, A7X, RWX, A4X, A1X, A6X
        1 Fanout(s)
            glb00.I7
        2 Product Term(s)
        2 GLB Level(s)

        GREEN_AR = (!CPURSTX
            # A4X & A6X & A7X & QX & !A1X & !A5X & !RWX & !A0X
            & _AND_846)
 

GLB glb12, A7

    10 Input(s)
        (AVMA.O, AVMAX, I8), (BA.O, BAX, I2), (E.O, EX, I5), (HSYNC.O,
        HSYNCX, I6), (MHZ28.O, MHZ28X, I15), (glb12.O3, N_134, I17),
        (Q.O, QX, I0), (RAS.O, RASX, I11), (VSYNC.O, VSYNCX, I10),
        (glb13.O0, WAVES, I12)
    4 Output(s)
        (_OR_973, O0), (N_78_QB, O1), (N_262_C, O2), (N_134, O3)
    11 Product Term(s)

    Output _OR_973

        5 Input(s)
            AVMAX, N_134, BAX, QX, EX
        1 Fanout(s)
            glb06.I3
        2 Product Term(s)
        2 GLB Level(s)

        _OR_973 = (N_134
            # EX & !AVMAX & !BAX & !QX)

    Output N_78_QB

        5 Input(s)
            HSYNCX, VSYNCX, QX, RASX, EX
        2 Fanout(s)
            glb07.I6, glb08.I6
        4 Product Term(s)
        1 GLB Level(s)

        N_78_QB.D = (QX
            # !EX
            # HSYNCX & VSYNCX)
            $ VCC
        !N_78_QB.C = RASX
        N_78_QB.R = RASX & !QX & !EX

    Output N_262_C

        6 Input(s)
            AVMAX, N_134, BAX, QX, MHZ28X, EX
        1 Fanout(s)
            glb03.I1
        2 Product Term(s)
        2 GLB Level(s)

        N_262_C = (MHZ28X & N_134
            # EX & MHZ28X & !AVMAX & !BAX & !QX)

    Output N_134

        6 Input(s)
            AVMAX, N_134, BAX, QX, WAVES, EX
        1 Fanout(s)
            glb12.I17
        2 Product Term(s)
        1 GLB Level(s)

        N_134 = (N_134 & !WAVES
            # EX & !WAVES & !AVMAX & !BAX & !QX)
 

GLB glb13, B7

    6 Input(s)
        (MHZ28.O, MHZ28X, I4), (glb06.O2, N_169, I9), (glb03.O3,
        N_262, I8), (glb10.O0, N_263, I12), (glb09.O0, N_264, I7),
        (SERINTHI.O, SERINTHIX, I11)
    4 Output(s)
        (WAVES, O0), (N_259, O1), (N_258, O2), (N_257, O3)
    1 Enable Output
        _BUF_1095
    6 Product Term(s)

    Output WAVES

        2 Input(s)
            MHZ28X, N_169
        2 Fanout(s)
            glb12.I12, glb05.I7
        1 Product Term(s)
        1 GLB Level(s)

        WAVES.D = N_169
        WAVES.C = MHZ28X

    Output N_259

        2 Input(s)
            MHZ28X, N_262
        1 Fanout(s)
            glb05.I6
        1 Product Term(s)
        1 GLB Level(s)

        N_259.D = N_262
        N_259.C = MHZ28X

    Output N_258

        2 Input(s)
            MHZ28X, N_263
        1 Fanout(s)
            glb05.I1
        1 Product Term(s)
        1 GLB Level(s)

        N_258.D = N_263
        N_258.C = MHZ28X

    Output N_257

        2 Input(s)
            MHZ28X, N_264
        1 Fanout(s)
            glb05.I0
        1 Product Term(s)
        1 GLB Level(s)

        N_257.D = N_264
        N_257.C = MHZ28X

    Enable Output _BUF_1095

        1 Input(s)
            SERINTHIX
        1 Fanout(s)
            INTSERLO.OE1
        1 Product Term(s)
        1 GLB Level(s)

        _BUF_1095 = SERINTHIX
 

Input A0, IO24

    Output A0X
        4 Fanout(s)
            glb01_part2.I3, glb11.I3, glb00.I8, glb04.I12
 

Input A1, IO61

    Output A1X
        4 Fanout(s)
            glb01_part2.I9, glb11.I9, glb00.I9, glb02.I9
 

Input A10, IO0

    Output A10X
        4 Fanout(s)
            glb02.I0, glb04.I15, glb07.I15, glb08.I15
 

Input A11, IO19

    Output A11X
        4 Fanout(s)
            glb02.I3, glb04.I8, glb07.I12, glb08.I12
 

Input A12, IO8

    Output A12X
        4 Fanout(s)
            glb02.I8, glb04.I7, glb07.I7, glb08.I7
 

Input A13, IO42

    Output A13X
        4 Fanout(s)
            glb02.I10, glb04.I5, glb07.I5, glb08.I5
 

Input A14, IO25

    Output A14X
        4 Fanout(s)
            glb02.I2, glb04.I6, glb07.I13, glb08.I13
 

Input A15, IO38

    Output A15X
        4 Fanout(s)
            glb02.I6, glb04.I9, glb07.I9, glb08.I9
 

Input A2, IO39

    Output A2X
        3 Fanout(s)
            glb02.I7, glb07.I8, glb08.I8
 

Input A3, IO33

    Output A3X
        4 Fanout(s)
            glb01_part2.I1, glb02.I1, glb07.I14, glb08.I14
 

Input A4, IO50

    Output A4X
        4 Fanout(s)
            glb01_part2.I2, glb11.I2, glb00.I2, glb04.I13
 

Input A5, IO22

    Output A5X
        4 Fanout(s)
            glb01_part2.I6, glb11.I13, glb00.I13, glb04.I2
 

Input A6, IO11

    Output A6X
        5 Fanout(s)
            glb01_part2.I0, glb11.I0, glb00.I0, glb04.I4, glb03.I15
 

Input A7, IO49

    Output A7X
        5 Fanout(s)
            glb01_part2.I5, glb11.I1, glb00.I1, glb04.I14, glb03.I14
 

Input A8, IO63

    Output A8X
        4 Fanout(s)
            glb02.I11, glb04.I0, glb07.I0, glb08.I0
 

Input A9, IO1

    Output A9X
        4 Fanout(s)
            glb02.I5, glb04.I10, glb07.I10, glb08.I10
 

Input AVMA, IO12

    Output AVMAX
        1 Fanout(s)
            glb12.I8
 

Input BA, IO2

    Output BAX
        1 Fanout(s)
            glb12.I2
 

Input BLK0, IO21

    Output BLK0X
        1 Fanout(s)
            glb00.I5
 

Input BLK1, IO16

    Output BLK1X
        1 Fanout(s)
            glb04.I11
 

Input CAS, IO34

    Output CASX
        1 Fanout(s)
            glb11.I6
 

Input CPU0, IO7

    Output CPU0X
        1 Fanout(s)
            glb03.I8
 

Input CPU1, IO15

    Output CPU1X
        1 Fanout(s)
            glb03.I0
 

Input CPURST, IO28

    Output CPURSTX
        3 Fanout(s)
            glb01_part2.I8, glb11.I8, glb03.I7
 

Input D0, IO60

    Output D0X
        2 Fanout(s)
            glb01_part2.I12, glb11.I12
 

Input D1, IO31

    Output D1X
        1 Fanout(s)
            glb11.I15
 

Output DELAY20NS, IO32

    Input (glb06.O0, _BUF_1105)

    DELAY20NS = _BUF_1105
 

Input E, IO5

    Output EX
        8 Fanout(s)
            glb00.I14, glb02.I14, glb01_part1.I5, glb12.I5, glb04.I1,
            glb05.I10, glb07.I1, glb08.I1
 

Output EOUT, IO35

    Input (glb05.O3, EOUT_PIN)

    EOUT = EOUT_PIN
 

Input FAST, IO46

    Output FASTX
        1 Fanout(s)
            glb05.I5
 

Output FF60_3, IO51

    Input (glb08.O3, _AND_865)

    FF60_3 = !_AND_865
 

Output FF64_7, IO58

    Input (glb08.O2, _AND_868)

    FF64_7 = !_AND_868
 

Output FF68_B, IO57

    Input (glb03.O1, _AND_970)

    FF68_B = !_AND_970
 

Output FF6C_F, IO52

    Input (glb08.O0, _AND_872)

    FF6C_F = !_AND_872
 

Output FFAXWR, IO26

    Input (glb01_part1.O2, _AND_971)

    FFAXWR = !_AND_971
 

Output GREEN_LED, IO3

    Input (glb00.O3, GREEN)

    GREEN_LED = !GREEN
 

Input HSYNC, IO6

    Output HSYNCX
        1 Fanout(s)
            glb12.I6
 

Input INPUT20NS, IO62

    Output INPUT20NSX
        1 Fanout(s)
            glb03.I5
 

Three-State Output INTSERLO, IO41

    Input (glb06.O1, _GND_1158)
    Enable (glb13.OE, _BUF_1095)

    INTSERLO = _GND_1158
    INTSERLO.E = !_BUF_1095
 

Output IORW, IO10

    Input (glb00.O2, _BUF_1106)

    IORW = _BUF_1106
 

Input MHZ28, IO47

    Output MHZ28X
        2 Fanout(s)
            glb12.I15, glb13.I4
 

Output NEWCAS, IO53

    Input (glb08.O1, NEWCAS_PIN)

    NEWCAS = NEWCAS_PIN
 

Output NEWRAS, IO48

    Input (glb07.O0, NEWRAS_PIN)

    NEWRAS = NEWRAS_PIN
 

Input Q, IO27

    Output QX
        7 Fanout(s)
            glb01_part2.I11, glb11.I11, glb00.I11, glb01_part1.I0,
            glb12.I0, glb05.I15, glb03.I4
 

Output QOUT, IO45

    Input (glb05.O1, QOUT_PIN)

    QOUT = QOUT_PIN
 

Output RAMADRS0, IO37

    Input (glb04.O1, RAMADRS0_PIN)

    RAMADRS0 = RAMADRS0_PIN
 

Output RAMADRS1, IO23

    Input (glb02.O3, RAMADRS1_PIN)

    RAMADRS1 = RAMADRS1_PIN
 

Output RAMADRS2, IO18

    Input (glb02.O2, RAMADRS2_PIN)

    RAMADRS2 = RAMADRS2_PIN
 

Output RAMADRS3, IO17

    Input (glb02.O1, RAMADRS3_PIN)

    RAMADRS3 = RAMADRS3_PIN
 

Input RAS, IO59

    Output RASX
        4 Fanout(s)
            glb12.I11, glb06.I15, glb07.I4, glb08.I4
 

Output RED_LED, IO40

    Input (glb05.O0, _AND_974)

    RED_LED = !_AND_974
 

Output RESHIGH, IO56

    Input (glb03.O0, _BUF_1103)

    RESHIGH = !_BUF_1103
 

Input RW, IO20

    Output RWX
        4 Fanout(s)
            glb01_part2.I15, glb11.I4, glb00.I4, glb01_part1.I4
 

Output SERIAL, IO36

    Input (glb04.O0, _OR_881)

    SERIAL = !_OR_881
 

Input SERINTHI, IO4

    Output SERINTHIX
        1 Fanout(s)
            glb13.I11
 

Output SIMM_A9, IO54

    Input (glb03.O2, _OR_972)

    SIMM_A9 = !_OR_972
 

Input VSYNC, IO30

    Output VSYNCX
        1 Fanout(s)
            glb12.I10
 

GLB and GLB Output Statistics

    GLB Name, Location      GLB Statistics          GLB Output Statistics
    GLB Output Name         Ins, Outs, PTs          Ins, FOs, PTs, Levels

        glb00, A3               13,  4,  7
            GREEN                                       10,  2,  0,  3
            _BUF_1106                                    1,  1,  1,  1
            _OR_863                                      5,  2,  2,  1
            _OR_875                                      5,  3,  2,  2

        glb01_part1, A5          4,  1,  1
            _AND_971                                     4,  1,  1,  3

        glb01_part2, A0         12,  1,  3
            N_68                                        12,  1,  1,  2

        glb02, A4               14,  4,  7
            RAMADRS1_PIN                                 3,  1,  2,  3
            RAMADRS2_PIN                                 3,  1,  2,  3
            RAMADRS3_PIN                                 3,  1,  2,  3
            _AND_857                                    10,  1,  1,  1

        glb03, B5               15,  4, 10
            N_262                                        3,  3,  1,  3
            _AND_970                                     2,  1,  1,  2
            _BUF_1103                                    1,  1,  1,  1
            _OR_972                                      9,  1,  5,  2

        glb04, B0               16,  4,  6
            RAMADRS0_PIN                                 3,  1,  2,  3
            _AND_874_part1                              10,  1,  1,  1
            _AND_874_part2                              10,  1,  1,  1
            _OR_881                                     14,  1,  2,  1

        glb05, B2                9,  4, 13
            EOUT_PIN                                     7,  1,  5,  1
            N_86                                         2,  1,  1,  1
            QOUT_PIN                                     7,  1,  5,  1
            _AND_974                                     2,  1,  1,  1

        glb06, B1                3,  3,  3
            N_169                                        2,  4,  0,  3
            _BUF_1105                                    1,  1,  1,  1
            _GND_1158                                    0,  1,  0,  0

        glb07, B4               13,  4,  4
            NEWRAS_PIN                                   3,  1,  2,  1
            _AND_846                                    11,  2,  1,  1
            _AND_850                                    11,  1,  1,  1
            _AND_854                                    11,  1,  1,  1

        glb08, B6               15,  4,  5
            NEWCAS_PIN                                   3,  1,  2,  2
            _AND_865                                    12,  1,  1,  2
            _AND_868                                    12,  1,  1,  2
            _AND_872                                    12,  1,  1,  2

        glb09, B3                3,  1,  3
            N_264                                        3,  3,  1,  1

        glb10, A2                3,  1,  3
            N_263                                        3,  3,  1,  1

        glb11, A1               14,  4,  7
            GREEN_AR                                    10,  1,  2,  2
            N_55                                        11,  1,  1,  2
            N_59                                        11,  1,  1,  2
            N_73                                         1,  1,  1,  1

        glb12, A7               10,  4, 11
            N_134                                        6,  1,  2,  1
            N_262_C                                      6,  1,  2,  2
            N_78_QB                                      5,  2,  4,  1
            _OR_973                                      5,  1,  2,  2

        glb13, B7                6,  4,  6
            N_257                                        2,  1,  1,  1
            N_258                                        2,  1,  1,  1
            N_259                                        2,  1,  1,  1
            WAVES                                        2,  2,  1,  1
 

Maximum-Level Trace

    GLB Level, Name, Ins    GLB Output Name

        3, glb00, 20            GREEN
        2, glb11                 GREEN_AR
        1, glb07                  _AND_846

        3, glb01_part1, 15      _AND_971
        2, glb00                 _OR_875
        1, glb04                  _AND_874_part1

        3, glb02, 16            RAMADRS3_PIN
        2, glb00                 _OR_875
        1, glb04                  _AND_874_part1

        3, glb02, 15            RAMADRS2_PIN
        2, glb00                 _OR_875
        1, glb04                  _AND_874_part1

        3, glb02, 15            RAMADRS1_PIN
        2, glb00                 _OR_875
        1, glb04                  _AND_874_part1

        3, glb03, 9             N_262
        2, glb12                 N_262_C
        1, glb12                  N_134

        3, glb04, 15            RAMADRS0_PIN
        2, glb00                 _OR_875
        1, glb04                  _AND_874_part1

        3, glb06, 7             N_169
        2, glb12                 _OR_973
        1, glb12                  N_134
 

Pin Assignments

    Pin Name                Pin Assignment          Pin Type, Pin Attribute

        NEWRAS                  3                       Output, SLOWSLEW
        A7                      4                       Input
        A4                      5                       Input
        FF60_3                  6                       Output, SLOWSLEW
        FF6C_F                  7                       Output, SLOWSLEW
        NEWCAS                  8                       Output, SLOWSLEW
        SIMM_A9                 9                       Output, CRIT
        RESHIGH                 11                      Output, SLOWSLEW
        FF68_B                  12                      Output, SLOWSLEW
        FF64_7                  13                      Output, SLOWSLEW
        RAS                     14                      Input
        D0                      15                      Input
        A1                      16                      Input
        INPUT20NS               17                      Input
        A8                      18                      Input
        A10                     26                      Input
        A9                      27                      Input
        BA                      28                      Input
        GREEN_LED               29                      Output
        SERINTHI                30                      Input
        E                       31                      Input
        HSYNC                   32                      Input
        CPU0                    33                      Input
        A12                     34                      Input
        IORW                    36                      Output, SLOWSLEW
        A6                      37                      Input
        AVMA                    38                      Input
        CPU1                    41                      Input
        BLK1                    45                      Input, PULLUP
        RAMADRS3                46                      Output, SLOWSLEW
        RAMADRS2                47                      Output, SLOWSLEW
        A11                     48                      Input
        RW                      49                      Input
        BLK0                    50                      Input, PULLUP
        A5                      51                      Input
        RAMADRS1                52                      Output, SLOWSLEW
        A0                      53                      Input
        A14                     54                      Input
        FFAXWR                  55                      Output, SLOWSLEW
        Q                       56                      Input
        CPURST                  57                      Input
        VSYNC                   59                      Input
        D1                      60                      Input
        DELAY20NS               68                      Output
        A3                      69                      Input
        CAS                     70                      Input
        EOUT                    71                      Output, PULLUP
        SERIAL                  72                      Output, SLOWSLEW
        RAMADRS0                73                      Output, SLOWSLEW
        A15                     74                      Input
        A2                      75                      Input
        RED_LED                 76                      Output
        INTSERLO                77                      Three-State Output
        A13                     78                      Input
        QOUT                    81                      Output, PULLUP
        FAST                    82                      Input, PULLUP
        MHZ28                   83                      Input
 

Design process management completed successfully
  1