"Deep in the sea are riches beyond compare.
But if you seek safety, it is on the shore."

BIOS GUIDE

Data Bus

· Single ALE Enable: Address Latch Enable (ALE) is an ISA Bus Signal (Pin B28) that indicates that a valid address is posted on the bus. The bus is used to communicate with 8 and 16 bit peripheral cards. Some chipsets have the capability to support an enhanced mode in which multiple ALE assertions may be made during a single Bus Cycle. Single ALE Enable apparently enables or disables that capability. May slow the video bus speed if enabled. Disabled (No) recommended.

· AT BUS Clock Selection (or AT Bus Clock Source): Gives a division of the CPU clock (or System Clock) so it can reach the ISA - EISA bus clock. An improper setting may cause significant decrease in performance. The settings are in terms of CLK/x, (or CLKIN/x and CLK2/x) where x may have values like 2, 3, 4, 5, etc. CLK represents your processor speed, with the exception that clock-multiple processors need to use the EXTERNAL clock rate, so a 486DX33, 486DX2/66, and 486DX3/99 all count as 33 and should have a divider value of 4. For 286 and 386 processors, CLK is half the speed of the CPU. You should try to reach 8.33 Mhz (that's the old bus clock of IBM AT; there may be cards which could do higher, but it's not highly recommended). On some motherboards, the AT bus speed is 7.15 Mhz. On new BIOS versions, there is an AUTO setting that will look at the clock frequency and determine the proper divider.

CLK /3 SX / DX16, DX 20, DX 25, DX2 / 50
CLK /4 SX / DX33, DX2 / 66, DX3 / 99
CLK /5 DX 40, DX2 / 80
CLK /6 DX 50, DX2 / 100

Selecting the right clock divider.

You can try other clock settings to increase performance. If you choose a too small divider (CLK/2 for a DX33) your system may hang. For a too big divider (CLK/5 for a DX33) the performance of ISA cards will decrease. This setting is for data exchange with ISA cards, NOT VL bus and PCI cards which run at CPU bus clock speeds: 25Mhz, 33Mhz and higher. If your ISA cards are fast enough to keep up, it is possible to run the bus at 12 Mhz. Note that if you switch crystals to overclock your CPU, you are also overclocking the ISA bus unless you change settings to compensate. Just because you can overclock the CPU doesn't mean you can get away with overclocking the ISA bus. It might just be one card that causes trouble, but one is enough. It might cause trouble even if you aren't using it by responding when it shouldn't.

· ISA Bus Speed: As above, but related for PCI.

· Bus Mode: It can be set in synchronous and asynchronous modes. In synchronous mode, the CPU clock is used, while in asynchronous mode the ATCLK is used.

· AT Cycle Wait State: Whenever an operation is performed with the AT bus, it indicates the number of wait states inserted. You may need some wait states if old ISA cards are used, notably if they are in operation with fast adapter cards.

· 16-bit Memory, I/O Wait State: The number of wait states before 16-bit memory and I/O operations.

· 8-bit Memory, I/O Wait State: As above, except this setting is for 8-bit operations.

· 16-bit I/O Recovery Time: The additional delay time inserted after every 16-bit operations. This value is added to the minimum delay inserted after every AT cycles.

· Fast AT Cycle: If enabled, may speed up transfer rates with ISA cards, notably video.

· ISA IRQ: Inform the PCI cards of the IRQs used by ISA cards, so they be discarded.

· DMA Wait States: The number of wait states inserted before direct memory access (DMA). The lower the better.

· DMA Clock Source: The source of the DMA clock for which some peripheral controllers, like floppy, tape, network and SCSI adapters use to address memory, which is 5 MHz maximum.

· E0000 ROM belongs to ATBUS: Tells if the E0000 area (upper memory) belongs to the MB DRAM or to the AT bus. Yes recommended.

· Memory Remapping: Remaps the memory used by the BIOS (A0000 to FFFF - 384 k) above the 1 Mb limit. If enabled you cannot shadow Video and System BIOS. Disabled recommended.

· Fast Decode Enable: Refers to some hardware that monitors the commands sent to the keyboard controller chip. The original AT used special codes not processed by the keyboard itself to control the switching of the 286 processor back from protected mode to real mode. The 286 had no hardware to do this, so they actually have to reset the CPU to switch back. This was not a speedy operation in the original AT, since IBM never expected that an OS might need to jump back and forth between real and protected modes. Clone makers added a few PLD chips to monitor the commands sent to the keyboard controller chip, and when the "reset CPU" code was seen, the PLD chips did an immediate reset, rather than waiting for the keyboard controller chip to poll its input, recognize the reset code, and then shut down the CPU for a short period. This "fast decode" of the keyboard reset command allowed OS/2 and Windows to switch between real and protected mode faster, and gave much better performance. (early 286 clones with Phoenix 286 BIOS had this setting to enable/disable the fast decode logic.) On 386 and newer processors, the fast decode is probably not used, since these CPUs have hardware instructions for switching between modes. There is another possible definition of the "Fast Decode Enable" command. The design of the original AT bus made it very difficult to mix 8-bit and 16-bit RAM or ROM within the same 128K block of high address space. Thus, an 8-bit BIOS ROM on a VGA card forced all other peripherals using the C000-Dfff range to also use 8 bits. By doing an "early decode" of the high address lines along with the 8/16 bit select flag, the I/O bus could then use mixed 8 and 16 bit peripherals. It is possible that on later systems, this BIOS flag controls the "fast decode" on these address lines.

· Extended I/O Decode: The normal range of I/O addresses is 0-0x3ff; 10 bits of I/O address space. Extended I/O-decode enables wider I/O-address bus. The CPU support a 64K I/O space, 16 address lines. Most motherboards or I/O adapters can be decoded only by 10 address bits.

· I/O Recovery Time: I/O recovery time is the number of wait states to be inserted between two consecutive I/O operations. It is generally specified as a two number pair -- e.g. 5/3. The first number is the number of wait states to insert on an 8 bit operation, the second the number of waits on a 16 bit operation. A few BIOSes specify an I/O Setup time (AT Bus (I/O) Command Delay). It is specified similarly to IO Recovery Time, but is a delay before STARTING an I/O operation rather than a delay BETWEEN I/O operations. 5/3 has been recommended as a value which will often yield a good combination of performance and reliability. When enabled, more I/O wait states are inserted. A transfer from IDE hard drive to memory happens without any handshaking, meaning the data has to be present (in the cache of the hard disk) when the CPU wants to read them from an I/O Port. This is called PIO (Programmed I/O) and works with a REP INSW assembler instruction. Now I/O Recovery Time enabled adds some wait states to this instruction. When disabled, the hard drive is a lot faster. Note that there is a connection between I/O Recovery Time and AT BUS Clock Selection. For example, if the AT BUS Clock is set to 8 MHz and you have a normal hard disk, I/O Recovery Time can be turned off, resulting in a higher transfer rate from hard disk.

· IDE Multi Block Mode: Enable IDE drives to transfer several sectors per interrupt. According to the hard drive cache size, six modes are possible. Mode 0 (standard mode transferring a single sector at a time), Mode 1 (no interrupts), Mode 2 (Sectors are transferred in a single burst), Mode 3 (32-bit instructions with speeds up to 11.1 Mb/sec.In BIOSes usually abbreviated as "32-bit mode". Not to be confused with 32-bit protected modeinstructions(!) or Windows' 32-bit disk access.), Mode 4 (up to 16,7 Mb/sec.) and Mode 5 (up to 20 Mb/sec.). The so-called "PIO mode 5" is completely bogus. It was launched by some controller manufacturers but was never accepted, never absorbed into the standards and you will not find any disk drives supporting it. Nor will you find any such drives in the future. The relevant parameter for block mode is the number of sectors per interrupt. The maximum number of sectors per interrupt is often (but not always) related to the drive's buffer size. If this setting is not set properly, communication with COM ports may not work properly. If the block size (sectors/interrupt) is set to too large a value, you may experience serial port overruns and CRC errors. To fix this, decrease the block size (preferred) or disable block mode altogether.

· IDE DMA Transfer Mode: Settings are Disabled, Type B (for EISA) and Standard (for PCI). Standard is the fastest but may cause problems with IDE CD ROM.

· IDE Multiple Sector Mode: When IDE DMA Transfer Mode is enabled, this sets the number of sectors per burst, with a maximum of 64. Problems may occur with COM ports.

- IDE Block Mode: Enables multi-sectors transfers.

Warning. This setting is known to cause crashes in Win95. Disabled recommended. Extremely annoying.

· IDE 32-bit Transfer: When enabled, the read / write rate of the hard disk is faster. When disabled only 16-bit data transfers is possible. The read/write rate of the harddisk stays the same, but the transfers over the host bus are maybe faster. So, don't expect anything really dramatic. Actually, you should ordinarily expect no difference at all, since even with 16-bit transfers, the local bus is fast enough to accomodate just about any disk drive. However, some interface hardware uses faster timing on the ATA (IDE) bus when 32-bit transfers are used. In those cases you may notice a speedup. Note that ATA (IDE) is a 16-bit bus. The 32-bit transfers referred to here are strictly the transfers between CPU and interface chip.

· Extended DMA Registers: Within a AT, DMA occurs for 16 Mb. When enabled, DMA covers the whole 4 Gb of a 32-bit processor.

Cacheing

· Cache Read Option: Often referred as "SRAM Read wait state" or "Cache Read Hit Burst" (SRAM: Static Random Access Memory). A specification of the number of clocks needed to load four 32-bit words into a CPU internal cache. Typically specified as clocks per word. 2-1-1-1 indicates 5 clocks to load the four words and is the theoretical minimum for current high end CPUs (486DX, 486SX, 486DX2, DX4, Pentium). Conceptually, the m-n-n-n notation is narrowly limited to CPUs supporting burst mode and with caches organized as 4 word "lines". However it would not be a surprise to see it extended to other CPU architectures. It takes simple integer values, like 2-1-1-1, 3-1-1-1 or 3-2-2-2. This determines the number of wait states for the cache RAM in normal and burst transfers (the latter for 486 only). The lower you computer can support, the better. 4-1-1-1 is usually recommended.

· Cache Write Option: Same thing as memory wait states, but according to cache ram.

· Fast Cache Read/Write: Enable if you have two banks of cache, 64K or 256K.

· Cache Wait State: Like conventional memory, the lower wait states for your cache, the better. 0 will give the optimal performance, but 1 wait state may be required for bus speed higher than 33 MHz.

· Tag Ram Includes Dirty: Enabling will cause an increase in performance, because the cache is not replaced during cycles, simply written over. It will usually cut the maximum cachable range in half, as one bit is taken off the address tag in order to be used as a dirty tag bit. So, if you have a lot of memory, you might be better off without dirty tag bit.

· Non-Cacheable Block-1 Size: Disabled. The Non-Cacheable region is intended for a memory-mapped I/O device that isn't supposed to be cached. For example, some video cards can present all video memory at 15 Mb - 16 Mb so software doesn't have to bank-switch. If the non-cacheable region covers actual RAM memory you are using, expect a significant performance decrease for accesses to that area. If the non-cacheable region covers only non-existent memory addresses, don't worry about it. If you don't want to cache some memory you can exclude 2 regions of memory. There are good reasons not to cache some memory areas. For example, if the memory area corresponds to some kind of buffer memory on a card so that the card may alter the contents of this buffer without warning the cache to invalidate the corresponding cache lines. Some BIOSes take more options than enabled /disabled, namely Nonlocal /Noncache /Disabled (VLB only?).

· Non-Cacheable Block-1 Base: 0KB. Enter the base address of the area you don't want to cache. It must be a multiple of the Non-Cacheable Block-1 Size selected.

· Non-Cacheable Block-2 Size: Disabled.

· Non-Cacheable Block-2 Base: 0KB.

· Cacheable RAM Address Range: Usually chipsets allow memory to be cached just up to 16 or 32 MB. This is to limit the number of bits of a memory address that need to be saved in the cache together with its contents. If you only have 4MB of RAM, select 4MB here. The lower the better, don't enter 16MB if you only have 8MB installed!

· Video BIOS Area Cacheable: To cache or not to cache video BIOS, a good question. You should try what is better - video access is faster with 'enabled', but cache has its size. With an "accelerated" video card it may be necessary to make the video RAM region non-cacheable so the CPU can see any changes the drawing engine makes in the frame buffer.

Memory

· Memory Read Wait State: (often referred as DRAM Wait States)The CPU is often much faster than the memory access time. On a 486, 1 or more wait states are often required for RAM with 80ns or higher access time. And, depending on the processor and motherboard, also for lower than 80ns access time. The less wait states, the better. Consult your manual. If wait states are too low, a parity error will occur. For 386 or 486 non-burst memory access cycle takes 2 clock ticks. A rough indication of RAM speed necessary for 0 wait states is 2000/Clock[MHz] - 10 [ns]. For a 33Mhz processor, this would give 50ns of access time required. The number of wait states necessary is approximately (RamSpeed[ns] +10) * Clock[MHz] /1000 - 2. For 70ns RAM and a 33Mhz processor (very standard configuration), this would give roughly 1 wait state. But this really is dependent on chipset, motherboard and cache design, CPU type and whether we talk about reads or writes. Take these formulas with a large grain of salt. You can find out the access time of your RAM chips by looking at their product numbers. Mostly at the end there is a 70, 80, 90, or even 60. If 10 stands there, it means 100 ns. Some RAM chips also have an explicitly written speed in ns. The RAM you buy these days mostly have 70ns or 60ns. Each wait states adds 30 ns of RAM access speed.

· Memory Write Wait State: Same as above.

In some BIOSes, these two options are combined as 'DRAM Wait State'. In that case, the number of read and write wait states is necessarily equal.

· DRAM CAS Timing Delay: The default is no CAS delay. DRAM is organized by rows and columns and accessed through strobes. Then a memory read/write is performed, the CPU activates RAS (Row Access Strobe) to find the row containing the required data. Afterwards, a CAS (Column Access Strobe) specifies the column. RAS and CAS are used to identify a location in a DRAM chip. RAS access is the speed of the chip while CAS is half the speed. When you have slow DRAM, you should use 1 state delay.

· DRAM Refresh Method: Selects the timing pulse width of RAS from RAS Only or CAS before RAS (which one is better?).

· RAS Precharge Time: Technically, this is the duration of the time interval during which the Row Address Strobe signal to a DRAM is held low during normal Read and Write Cycles. This is the minimum interval between completing one read or write and starting another from the same (non-page mode) DRAM. Techniques such as memory interleaving, or use of Page Mode DRAM are often used to avoid this delay. Some chipsets require this parameter in order to set up the memory configuration properly. The RAS Precharge value is typically about the same as the RAM Access (data read/write) time. The latter can be used as an estimate if the actual value is unavailable. At least one BIOS describes the precharge and access times as RAS LOW and RAS HIGH Times. For a 33 MHz CPU, 4 is a good choice, while lower values should be selected for slower speeds.

· RAS Active Time: The amount of time a RAS can be kept open for multiple accesses. High figures will improve performance.

· RAS to CAS Delay Time: Amount of time a CAS is performed after a RAS. The lower the better, but some DRAM will not support low figures.

· CAS Before RAS: Reduces refresh cycles and power consumption.

· CAS Width in Read Cycle: The number of wait states for the CPU to read DRAM. The lower the better.

· Interleave Mode: Controls how the CPU access different DRAM banks.

· Fast Page Mode DRAM: This speeds up memory access for DRAM capable of handling it (most do). When access occurs in the same memory area, RAS and CAS are not necessary.

Plug and Play/PCI
A system intended to make fitting of expansion cards easier (yes, really!). In this context, ISA cards are known as Legacy Cards, and are switched as normal to make them fit in. Have as few of these as possible, as accesses to them are slow. With Concurrent PCI, The T II (or 430HX/VX) chipset's Multi Transaction Timer allows multiple transfers in one PCI request, by reducing re-arbitration when several PCI processes can take place at once. Passive Release allows the PCI bus to continue working when it's receiving data from ISA devices, which would normally hog the bus. Delayed Transaction allows PCI bus masters to work by delaying transmissions to ISA cards. Write merging combines byte, word and Dword cycles into a single write to memory.

The idea is that plug and play cards get interrogated by the system they are plugged into, and their requirements checked against those of the cards already in there. The BIOS will feed the data as required to the Operating System, typically Windows '95. Here you will be able to assign IRQs, etc to PCI slots and map PCI INT#s to them. Although Windows '95 or a PnP BIOS can do a lot by themselves, you really need the lot, e.g.a Plug and Play BIOS, with compatible devices and an Operating System for the best performance. Be aware that not all PCI (2.0) cards are PnP. PC (PCMCIA) cards are also "Plug and Play", but are not considered here.

PnP itself was originally devised by Compaq, Intel and Phoenix. Your chipset settings may allow you to choose of two methods of operation:

All PnP devices are configured and activated.
All PnP ISA cards are isolated and checked, but only those needed to boot the machine are activated. The ISA system cannot produce specific information about a card, so the BIOS has to isolate each one and give it a temporary handle so its requirements can be read. Resources can be allocated once all cards have been dealt with (recommended for Windows '95, as it can use the Registry and its own procedures to use the same information every time you boot).
ESCD (Extended System Configuration Data), a system which is part of PnP (actually a superset of EISA), that can store data on PnP or non-PnP EISA, ISA or PCI cards to perform the same function as the Windows '95 Registry above, that is, provide consistency between sessions. It occupies part of Upper Memory (E000-EDFF), which is not available to memory managers. The default length is 4K, and problems have been reported with EMS buffer addressing when this area has been used.

PCI Slot Configuration

Although an unlimited number of PCI slots is allowed, in practice 4 is the maximum, due to loading considerations.PCI cards and slots use an internal interrupt system, with each slot being able to activate up to 4, labelled either INT#A-INT#D, or INT#1-INT#4. These are nothing to do with IRQs, although they can be mapped to them if the card concerned needs it. Typically IRQs 9 and 10 are reserved for this, but any available ones can be used.

Latency Timer (PCI Clocks). Controls the length of time an agent on the PCI bus can hold the bus when another has requested it, so everything gets its fair share.Since the PCI bus runs faster than the ISA bus, the PCI bus must be slowed during interactions with it. This setting allows you to define how long the PCI bus will delay for a transaction between the given PCI slot and the ISA bus. This number is dependent on the PCI master device in use and varies from 0 to 255. AMI defaults to 66, but 40 clocks is a good place to start at 33MHz (Phoenix). The shorter the value, the more rapid access to the bus a device gets, with better response times, but the lower becomes the effective bandwidth and hence data throughput. Normally, leave this alone, but you could set it to a lower value if you have latency sensitive cards (e.g. audio cards and/or network cards with small buffers). Increase slightly if I/O sensitive applications are being run.
Using IRQ. Affected by the Trigger method. With PCI, you assign IRQs, etc to a slot, rather than adjusting the card, but only if the card needs an IRQ. There are two methods of IRQ usage, Level or Edge triggered (see Expansion Cards). Most PCI cards use the former, and ISA the latter.

PCI Slot x INTx. Assigns PCI INT#s to slots 1/2/3 (or whatever). See Slot X using INT#, overleaf.

Edge/Level Select. Programs PCI IRQs to single-edge or logic level. Level or Edge sensitivity is programmed per controller. Select Edge for PCI IDE.

PCI Device, Slot 1/2/3. Enables I/O and memory cycle decoding.

Enable. As slave

En Master. Enables PCI device as bus master.

Use Default Latency Timer Value. If yes, you don't need Latency Timer (above).

Slot X Using INT#. Selects an INT# channel for a PCI Slot, and there are four (A, B, C & D) for each one, that is, each PCI bus slot supports interrupts A, B, C and D. #A is allocated automatically, and you would only use #B, #C, etc if the card needs to use more than one (PCI) interrupt service. For example, select #D if your card needs four. Using Auto is simplest. Most graphics cards don't need this.
Xth Available IRQ. Selects (or maps) an IRQ for one of the available INT#s above. There are ten selections (3, 4, 5, 6, 7, 9, 10, 11, 12, 14, 15). 1st available IRQ means the BIOS will assign this IRQ to the first PCI slots (order is 1, 2, 3, 4). NA means the IRQ has been assigned to the ISA bus and is therefore not available to a PCI slot.
1st-6th Available IRQ. As above.
PCI IRQ Activated by. The method by which the PCI bus recognises an IRQ request; Level or Edge (see Expansion Cards). Use the default unless advised otherwise by your manufacturer or if you have a PCI device which only recognizes one of them.
Configuration Mode. Sets the method by which information about legacy cards is conveyed to the system.
Use ICU--the BIOS depends on information provided by Plug and Play software (e.g. Configuration Manager or ISA Configuration Utility). Only set this if you have the utilities concerned.

Use Setup Utility. The BIOS depends on information provided by you in the following settings. Don't use the above utilities.

ISA Shared Memory Size. Sets a block of system memory which will not be shadowed. Should be disabled, unless you have an ISA card that uses the upper memory area. If you use this setting you will also get the following:
ISA Shared Memory Base Address. If you choose 64K, you can only choose D000 or below.

IRQ 3-IRQ 15. Used to indicate what IRQs are in use by ISA Legacy cards. If not used, set to Available. Otherwise, set Used by ISA Card, which means that nothing else can use it.
PCI IDE Prefetch Buffers. Disables a set of prefetch buffers in the PCI IDE controller. You may need to do this with an operating system (like NT) that doesn't use the BIOS to access the hard disk and doesn't disable interrupts when completing a programmed I/O operation. Disabling also prevents errors with faulty PCI-IDE interface chips that can corrupt data on the hard disk (with true 32-bit operating systems). Check if you've got a PC-Tech RZ1000 or a CMD PCIO 640, but disabling is done automatically with later boards.
PCI IDE 2nd Channel. Disable this if you're not using the 2nd channel on the PCI IDE card, or you will lose IRQ 15 on the ISA slots.
PCI IDE IRQ Map to. Allows you to configure your system to the type of IDE disk controller; an ISA device is assumed. The more apparent difference is the type of slot being used. However, if you have a PCI IDE controller, this setting allows you to specify which slot has the controller and which PCI INT# (A, B,C or D) is associated with the connected hard drives. Note that this refers to the hard disk rather than individual partitions. Since each IDE controller supports two drives, you can select the INT# for each. Note also that the primary has a lower interrupt than the secondary, as described in Slot x Using INT#.
PCI-Auto. If the IDE is detected by the BIOS on one of the PCI slots, then the apropriate INT# channel will be assigned to IRQ 14.

PCI-Slot X. If the IDE is not detected, youn can manually select the slot.

Primary IDE INT#, Secondary IDE INT#. Assigns 2 INT channels for primary and secondary channels, if supported.

ISA. Assigns no IRQs to PCI slots. Use for PCI IDE cards that connect IRQs 14 and 15 directly from an ISA slot using a table from a legacy paddleboard.

PCI Bus Parking. Sort of bus mastering; a device parking on the PCI Bus has full control of the bus for a short time. Improves performance when that device is being used, but excludes others. Try with NICs and Hard Disk Controllers.
IDE Buffer for DOS & Win. For IDE read ahead and posted write buffers, so you can increase throughput to and from IDE devices by buffering reads and writes. Slower IDE devices could end up slower, though.
IDE Master (Slave) PIO Mode. Changes IDE data transfer speed; Mode 0-4, or Auto. PIO means Programmed Input/Output. Rather than have the BIOS issue commands to effect transfers to or from the disk drive, PIO allows the BIOS to tell the controller what it wants, and then lets the controller and the CPU perform the complete task by themselves. Modes 1-4 are available.
HCLK PCICLK. Host CLK vs PCI CLK divider; AUTO, 1-1, 1-1.5.
PCI-ISA BCLK Divider. PCI Bus CLK vs ISA Bus CLK divider; AUTO, PCICLK1/3, PCICLK1/2, PCICLK1/4.
CPU to PCI Byte Merge. See Byte Merging for explanation (below).
PCI Write-byte-Merge. When enabled, this allows data sent from the CPU to the PCI bus to be held in a buffer. The chipset will then write the data in the buffer to the PCI bus when appropriate.
CPU-to-PCI Read Buffer. When enabled, up to four Dwords can be read from the PCI bus without interrupting the CPU. When disabled, a write buffer is not used and the CPU read cycle will not be completed until the PCI bus signals that it is ready to receive the data. The former is best for performance.
PCI-to-CPU Write Buffer. See above.
CPU-to-PCI Read-Line. When On, more time will be allocated for data setup with faster CPUs. This may only be required if you add an Intel OverDrive processor to your system.
CPU-to-PCI Read-Burst. When enabled, the PCI bus will interpret CPU read cycles as the PCI burst protocol, meaning that back-to-back sequential CPU memory read cycles addressed to the PCI will be translated into fast PCI burst memory cycles. Performance is improved, but some non-standard PCI adapters (e.g. VGA) may have problems.
PCI to DRAM Buffer. Improves PCI to DRAM performance by allowing data to be stored if a destination is busy.Buffers are needed because the PCI bus is divorced from the CPU.
Latency for CPU to PCI write. Delay time before CPU writes data to the PCI bus.
PCI Cycle Cache Hit WS. Similar to above. With the latter, the CPU has less to do, so performance is better.
Normal--Cache refresh during normal PCI cycles.

Fast--Cache refresh without PCI cycle for CAS.

Use Default Latency Timer Value. Whether or not the default value for the Latency Timer will be loaded, or the succeeding Latency Timer Value will be used. If Yes is selected (default), no further programming is needed in the Latency Timer Value option (below).
Latency Timer Value. The maximum number of PCI bus clocks that the master may burst. A longer latency time gives the CPU more of a chance to control the bus. See also Latency Timer (PCI Clocks).
Latency from ADS# status. This allows you to configure how long the CPU waits for the Address Data Status (ADS). It determines the CPU to PCI Post write speed. When set to 3T, this is 5T for each double word. With 2T (default), it is 4T per double word. For a Qword PCI memory write, the rate is 7T (2T) or 8T (3T). The default should be OK, but if you add a faster CPU to your system, you may find it necessary to increase it. The choices are:
3T--Three CPU clocks

2T--Two CPU clocks (Default)

PCI Master Latency. If your PCI Master cards control the bus for too long, there is less time for the CPU to control it. A longer latency time gives the CPU more of a chance. Don't use zero.
Max burstable range. The maximum bursting length for each FRAME# asserting. FRAME# is an electrical signal. Dunno what it does, yet.
CPU to PCI burst memory write. If enabled, back-to-back sequential CPU memory write cycles to PCI are translated to PCI burst memory write cycles. Otherwise, each single write to PCI will have an associated FRAME# sequence. Enabled is best for performance, but some non-standard PCI cards (e.g. VGA) may have problems.
Fast Back To Back. Possibly as above, but working on it!
CPU to PCI post memory write. Enabling allows up to 4 Dwords of data to be posted to PCI. Otherwise, not only is buffering disabled, completion of CPU writes is limited (e.g. CPU write does not complete until the PCI transaction completes). Enabled is best for performance.
CPU to PCI Write Buffer. As above. Buffers are needed because the PCI bus is divorced from the CPU; they improve overall system performance by allowing the processor (or bus master) to do what it needs without writing data to its final destination; the data is temporarily stored in fast buffers.
PCI to ISA Write Buffer. When enabled, the system will temporarily write data to a buffer so the CPU is not interrupted. When disabled, the memory write cycle for the PCI bus will be direct to the slower ISA bus. The former is best for performance.
DMA Line Buffer. Allows DMA data to be stored in a buffer so PCI bus operations are not interrupted. Disabled means that the line buffer for DMA is in single transaction mode. Enabled allows it to operate in an 8-byte transaction mode for greater efficiency.
ISA Master Line Buffer. ISA master buffers are designed to isolate the slower ISA I/O operations from the PCI bus for better performance. Disabled means the buffer for ISA master transaction is in single mode. Enabled means it is in 8-byte mode, increasing the ISA master's performance.
CPU/PCI Post Write Delay. Delay time before the CPU writes data into the PCI bus.
Post Write CAS Active. Pulse width of CAS# when the PCI master writes to DRAM.
PCI master accesses shadow RAM. Enables the shadowing of a ROM on a PCI master for better performance.
Enable Master. Enables the selected device as a PCI bus master and checks whether the card is so capable.
AT bus clock frequency. AT bus speed in a PCI system. Choose whatever divisor gives you a speed of 6-8.33 MHz, depending on the speed of the PCI bus.
ISA Bus Clock Frequency. As above.
Base I/O Address. The base of the I/O address range from which the PCI device resource requests are satisfied.
Base Memory Address. The base of the 32-bit memory address range from which the PCI device resource requests are satisfied.
Parity. Allows parity checking of PCI devices.
ISA Linear Frame Buffer. Set to the appropriate size if you use an ISA card that features a linear frame buffer (e.g. a second video card for ACAD). The address will be set automatically.
ISA VGA Frame Buffer Size. This is to help you use a VGA frame buffer and 16 Mb of RAM at the same time; the system will allow access to the graphics card through a hole in its own memory map; in other words, accesses made to addresses within this hole will be directed to the ISA bus instead of main memory. Should be set to Disabled, unless you are using an ISA card with more than 64K of memory that needs to be accessed by the CPU, and you are not using the Plug and Play utilities. If you have less than 8 Mb memory, or use MS-DOS, this will be ignored.
Residence of VGA Card. Whether on PCI or VL Bus.
ISA LFB Size. LFB=Linear Frame Buffer. See above.
Memory Map Hole; Memory Map Hole Start/End Address. See ISA VGA Frame Buffer Size. Where the hole starts depends on ISA LFB Size. Sometimes this is informative only. If you can change it, base address should be 16Mb, less buffer size.
Memory Hole Size. Options include 1 Mb, 2 Mb, 4 Mb, 8 Mb, Disabled. These are the amounts below 1 Mb assigned to the AT Bus, and reserved for ISA cards.
Memory Hole Start Address. To improve performance, certain parts of memory are reserved for ISA cards, which must be mapped into the memory space below 16 MB for DMA reasons. The selections are from 1-15 with each number in Mb. This is irrelevant if the memory hole is disabled (see above).
Memory Hole at 15-16M. See above.
Local Memory 15-16M. To increase performance, you can map slower device memory (e.g. on the ISA bus) into much faster local bus memory. Local memory is set aside and the start point transferred from the device memory to local memory. The default is enabled.
15-16M Memory Location. The area in the memory map allocated for ISA option ROMs. Choices are Local (default) or Non-local.
Byte Merging. This exists where writes to sequential memory addresses are merged into one PCI-to-memory operation, which increases performance for older applications that write to video memory in bytes rather than words--not supported on all PCI video cards. Enable unless you get bad graphics. See also next for a variation.
Byte Merge Support. 8- or 16-bit data en route from the CPU to the PCI bus is held in a buffer where it is accumulated, or merged, into 32-bit data, giving faster performance. In this case, enabling means that CPU-PCI writes are buffered (Award).
Multimedia Mode. Enables or disables palette snooping for multimedia cards.
Video Palette Snoop. Controls how a PCI graphics card can "snoop" write cycles to an ISA video card's colour palette registers. Snooping essentially means interfereing with a device.Only set to Disabled if:
An ISA card connects to a PCI graphics card through a VESA connector

The ISA card connects to a colour monitor, and

The ISA card uses the RAMDAC on the PCI card, and

Palette Snooping (RAMDAC shadowing) not operative on PCI card.

PCI/VGA Palette Snoop. Alters the VGA palette setting while graphic signals pass through the feature connector of PCI VGA card and are processed by MPEG card. Enable if you have MPEG connections through the VGA feature connector; this means you can adjust PCI/VGA palettes. VGA snooping is used by multimedia video devices (e.g. video capture boards) to look ahead at the video controller (VGA device) to see what color palette is currently in use. It is only in exceptional circumstances that you might ever need to enable this, so disable for ordinary systems. (Award BIOS).
Snoop Filter. Saves the need for multiple enquiries to the same line if it was inquired previously. When enabled, cache snoop filters ensure data integrity (cache coherency) while reducing the snoop frequency to a minimum.
E8000 32K Accessible. The 64K E area of upper memory is used for BIOS purposes on PS/2s, 32 bit operating systems and Plug and Play. This setting allows the second 32K page to be used for other purposes when not needed, in the same way that the first 32K page of the F range is useable after boot up has finished.
P5 Piped Address. Default is Disabled
PCI Arbiter Mode. Devices gain access to the PCI bus through arbitration. There are two modes, 1 (the default) and 2. The idea is to minimize the time it takes to gain control of the bus and move data. Generally, Mode 1 should be sufficient, but try mode 2 if you get problems.
Stop CPU When Flush Assert. See below.
Stop CPU when PCI Flush. When enabled, the CPU will be stopped when the PCI bus is being flushed of data. Disabling (default) allows the CPU to continue processing, giving greater efficiency.
Stop CPU at PCI Master. When enabled, the CPU will be stopped when the PCI bus master is operating on the bus. Disabling (default) allows the CPU to carry on, giving greater efficiency.
I/O Cycle Recovery. When enabled, the PCI will be allowed a recovery period for back-to-back I/O, which slows back-to-back data transfers; it's like adding wait states, so disable (default) for best performance.
I/O Recovery Period. Sets the length of time of the recovery cycle used above. The range is from 0-1.75 microseconds in 0.25 microsecond intervals.
Action When W_Buffer Full. Sets the behaviour of the system when the write buffer is full. By default the system will immediately retry, rather than wait for it to be emptied.
Fast Back-to-Back. When enabled, the PCI bus will interpret CPU read cycles as the PCI burst protocol, meaning that back-to-back sequential CPU memory read cycles addressed to the PCI will be translated into the fast PCI burst memory cycles. Default is enabled.
CPU Pipelined Function. This allows the system controller to signal the CPU for a new memory address, even before all data transfers for the current cycle are complete, resulting in increased throughput. The default is Disabled, that is, pipelining off.
Primary Frame Buffer. When enabled, this allows the system to use unreserved memory as a primary frame buffer. Unlike the VGA frame buffer, this would reduce overall available RAM for applications.
M1445RDYJ to CPURDYJ. Whether the PCI Ready signal is to be synchronized by the CPU clock's ready signal or bypassed (default).
VESA Master Cycle ADSJ. Allows you to increase the length of time the VESA Master has to decode bus commands. Choices are Normal (default) and Long.
LDEVJ Check Point Delay. This allows you to select how much time is allocated for checking bus cycle comands. These commands must be decoded to determine whether a local bus device access signal (LDEVJ) is being sent, or an ISA device is being addressed. Increasing the delay increases stability, especially the VESA sub-system while very slightly degrading the performance of the ISA sub-system. Settings are in terms of the feedback clock rate (FBCLK2) used in the cache/memory control interface.
1 FBCLK2=One clock
2 FBCLK2=Two clocks (Default)
3 FBCLK2=Three clocks
CPU Dynamic-Fast-Cycle. Gives you faster access to the ISA bus. When the CPU issues a bus cycle, the PCI bus examines the command to determine if a PCI agent claims it. If not, then an ISA bus cycle is initiated. The Dynamic-Fast-Access then allows for faster access to the ISA bus by decreasing the latency (or delay) between the original CPU command and the beginning of the ISA cycle.
CPU Memory sample point. This allows you to select the cycle check point, which is where memory decoding and cache hit/miss checking takes place. Each selection indicates that the check takes place at the end of a CPU cycle, with one wait state indicating more time for checking to take place than zero wait states. A longer check time allows for greater stability at the expense of some speed.
LDEV# Check point. The VESA local device (LDEV#) check point is where the VL-bus device decodes the bus commands and error checks, within the bus cycle itself.
0 Bus cycle point T1 (Default)
1 During the first T2
2 During second T2
3 During third T2
Local memory check point. Allows you to select between two techniques for decoding and error checking local bus writes to DRAM during a memory cycle.
Slow=Extra wait state; better checking (default).

Fast=No extra wait state used.

FRAMEJ generation. When the PCI-VL bus bridge is acting as a PCI Master and receiving data from the CPU, a fast CPU-to-PCI buffer will be enabled if this selection is also enabled. Using the buffer allows the CPU to complete a write even though the data has not been delivered to the PCI bus. This reduces the number of CPU cycles involved and speeds overall processing.
Normal Buffering not employed (Default)

Fast Buffer used for CPU-to-PCI writes.

PCI to CPU Write Pending. Sets the behaviour of the system when the write buffer is full. By default, the system will immediately retry, but you can set it to wait for the buffer to be emptied before retrying.
Delay for SCSI/HDD (Secs). The length of time in seconds the BIOS will wait for the SCSI hard disk to be ready for operation. If the hard drive is not ready, the PCI SCSI BIOS might not detect the hard drive correctly. The range is from 0-60 seconds.
Master IOCHRDY. Enabled, allows the system to monitor for a VESA master request to generate an I/O channel ready (IOCHRDY) signal.
VGA Type. This data is used when the video bios is being shadowed. The BIOS uses this information to determine which bus to use. Choices are Standard (default), PCI, ISA/VESA.
PCI Mstr Timing Mode. This system supports two timing modes, 0 (default) and 1.
PCI Arbit. Rotate Priority. Typically, the system manages or arbitrates access to the PCI bus on a first-come-first-served basis. When priority is rotated, once a device gains control of the bus it is assigned the lowest priority and every other device is moved up one in the priority queue.
I/O Cycle Post-Write. When Enabled (default), data being written during an I/O cycle will be buffered for faster performance.
PCI Post-Write Fast. As in the above I/O Cycle Post-Write, enabling this will allow the system to use a fast memory buffer for writes to the PCI bus.
CPU Mstr Post-WR Buffer. When the CPU operates as a bus master for either memory access or I/O, this item controls its use of a high speed posted write buffer. Choices are NA, 1, 2 and 4 (default).
CPU Mstr Post-WR Burst Mode. When the CPU operates as a bus master for either memory access or I/O, this item controls its ability to use a high speed burst mode for posted writes to a buffer.
CPU Mstr Fast Interface. This enables/disables what is known as a fast back-to-back interface when the CPU operates as a bus master. When enabled, consecutive reads/writes are interpreted as the CPU high-performance burst mode.
PCI Mstr Post-WR Buffer. When a PCI device operates as a bus master for either memory access or I/O, this item controls its use of a high speed posted write buffer. Choices are NA, 1, 2 and 4 (default).
PCI Mstr Burst Mode. When a PCI device operates as a bus master for either memory access or I/O, this item controls its ability to use a high speed burst mode for posted writes to a buffer.
PCI Mstr Fast Interface. This enables/disables what is known as a fast back-to-back interface when a PCI device operates as a bus master. When enabled, consecutive reads/writes are interpreted as the PCI high-performance burst mode.
CPU Mstr DEVSEL# Time-out. When the CPU initiates a master cycle using an address (target) which has not been mapped to PCI/VESA or ISA space, the system will monitor the DEVSEL (device select) pin for a period of time to see if any device claims the cycle. This item allows you to determine how long the system will wait before timing-out. Choices are 3 PCICLK, 4 PCICLK, 5 PCICLK and 6 PCICLK (default).
PCI Mstr DEVSEL# Time-out. When a PCI device initiates a master cycle using an address (target) which has not been mapped to PCI/VESA or ISA space, the system will monitor the DEVSEL (device select) pin for a period of time to see if any device claims the cycle. This item allows you to determine how long the system will wait before timing-out. Choices are 3 PCICLK, 4 PCICLK (default), 5 PCICLK and 6 PCICLK.
IRQ Line. If you have installed a device requiring an IRQ service into the given PCI slot, use this item to inform the PCI bus which IRQ it should initiate. Choices range from IRQ 3 through IRQ 15.
Fast Back-to-Back Cycle. When enabled, the PCI bus will interpret CPU read or write cycles as PCI burst protocol, meaning that back-to-back sequential CPU memory read/write cycles addressed to the PCI will be translated into fast PCI burst memory cycles.
State Machines. The chipset uses four state machines to manage specific CPU and/or PCI operations. Each can be thought of as a highly optimized process center designed to handle specific operations. Generally, each operation involves a master device and the bus it wishes to employ. The four state machines are:
CPU master to CPU bus (CC)
CPU master to PCI bus (CP)
PCI master to PCI bus (PP)
PCI master to CPU bus (PC)
Each have the following settings:

Address 0 WS. This refers to the length of time the system will delay while the transaction address is decoded. Enabled=no delay.

Data Write 0 WS. The length of time the system will delay while data is being written to the target address. When Enabled, there will be no delay.

Data Read 0 WS. The length of time the system will delay while data is being read from the target address. When Enabled, there will be no delay.

On Board PCI/SCSI BIOS. You would enable this if your system motherboard had a built-in SCSI controller attached to the PCI bus, and you wanted to boot from it.
PCI I/O Start Address. I/O devices make themselves accessible by occupying an address space. This allows you to make additional room for older ISA devices by defining the I/O start address for the PCI devices.
Memory Start Address. This is for devices with their own memory which use part of the CPU's memory address space, allowing you to determine the starting point in memory where PCI device memory will be mapped.
VGA 128k Range Attribute. When enabled, this allows the chipset to apply features like CPU-TO-PCI Byte Merge, CPU-TO-PCI Prefetch to be applied to VGA memory range A0000H-BFFFFH.
Enabled=VGA receives CPU-TO-PCI functions.

Disabled=Retain standard VGA interface.

CPU-To-PCI Write Posting. The Orion chipset maintains its own internal read and write buffers which are used to help compensate for the speed differences between the CPU and the PCI bus. When this is Enabled, writes from the CPU to the PCI bus will be buffered. When Disabled (default), the writes will not be buffered and the CPU will be forced to wait until the write is completed.
CPU Read Multiple Prefetch. A prefetch occurs during a process (e.g. reading from the PCI or memory) when the chipset peeks at the next instruction and actually begins the next read. The Orion chipset has four read lines. A multiple prefetch means the chipset can initiate more than one prefetch during a process. Default is Disabled.
CPU Line Read Multiple. A line read means that the CPU is reading a full cache line. When a cache line is full it holds 32 bytes (eight DWORDS) of data. Because the line is full, the system knows exactly how much data it will be reading and doesn't need to wait for an end-of-data signal, freeing it to do other things. When this is enabled, the system is allowed to read more than one full cache line at a time. The default is disabled.
CPU Line Read Prefetch. See above. When this is enabled, the system is allowed to prefetch the next read instruction and initiate the next process.
CPU Line Read. This Enables or Disables (default) full CPU line reads.
CPU Burst Write Assembly. The (Orion) chipset maintains four posted write buffers. When this is enabled, the chipset can assemble long PCI bursts from the data held in them. Default is Disabled.
VGA Performance Mode. If enabled, the VGA memory range of A 0000-B 0000 will use a special set of performance features. This has little or no effect using video modes beyond the standard VGA most commonly used for Windows, OS/2, UNIX, etc, but this memory range is heavily used by games such as DOOM.
Snoop Ahead. This is only applicable if the cache is enabled. When enabled, PCI bus masters can monitor the VGA palette registers for direct writes and translate them into PCI burst protocol for greater speed, to enhance the performance of multimedia video.
DMA Line Buffer Mode. This allows DMA data to be stored in a buffer so as not to interrupt the PCI bus. When Standard is selected, the line buffer is in single transaction mode. Enhanced allows it to operate in 8-byte transaction mode.
Master Arbitration Protocol. This is the method by which the PCI bus determines which bus master device gains access to it.
PCI Clock Frequency. Allows you to set the clock rate for the PCI bus, which can operate between 0-33 Mhz. CPUCLK/3 means the PCI bus was operating at 11 Mhz (33/3 = 11).
CPUCLK/1.5 CPU speed / 1.5 (Default)
CPUCLK/3 CPU speed/3
14 Mhz 14 Mhz
CPUCLK/2 CPU speed/2
Max, Burstable Range. Sets the size of the maximum range of contiguous memory which can be addressed by a burst from the PCI bus, a half or one K.
ISA Bus Clock Frequency. Allows you to set the speed of the ISA bus in fractions of the PCI bus speed, so if the PCI bus is operating at its theoretical maximum, 33 Mhz, PCICLK/3 would yield an ISA speed of 11 Mhz.
7.159 Mhz (default)
PCICLK/4 A quarter speed of the PCI bus
PCICLK/3 One third speed of the PCI bus
8 Bit I/O Recovery Time. The recovery time is the length of time, measured in CPU clocks, which the system will delay after the completion of an input/output request to the ISA bus, needed because the CPU is running faster than the bus, and needs to be slowed down. Clock cycles are added to a minimum delay (usually 5) between PCI-originated I/O cycles to the ISA bus. Choices are from 1 to 7 or 8 CPU clocks. 1 is the default.
16 Bit I/O Recovery Time. As above, for 16 bit I/O. Choices are from 1 to 4 CPU clocks. 1 is the default.
I/O Recovery Time. A programmed delay which allows the PCI bus to exchange data with the slower ISA bus without data errors. Settings are in fractions of the PCI BCL:
2 BCLK=Two BCLKS (default)
4 BCLK=Four BCLKS
8 BCLK=Eight BCLKS
12 BCLK=Twelve BCLKS
PCI Concurrency. Enabled (default) means that more than one PCI device can be active at a time (Award). With Intel Chipsets, it allocates memory bus cycles to a PCI controller while an ISA operation, such as bus mastered DMA, is taking place, which normally requires constant attention. This involves turning on additional read and write buffering in the chipset. The PCI bus can also obtain access cycles for small data transfers without the delays caused by renegotiatiating bus access for each part of the transfer, so is meant to improve performance and consistency.
PCI Streaming. Data is typically moved to and from memory and between devices in discrete chunks of limited sizes, because the CPU is involved. On the PCI bus, data can be streamed, that is, much larger chunks can be moved without the CPU being bothered. Enable for best performance.
PCI Bursting. Consecutive writes from CPU will be regarded as a PCI Burst cycle. Enable = best performance; some cards might not like it.
PCI (IDE) Bursting. As above, but this one enables burst mode access to video memory over the PCI bus. The CPU provides the first address, and consecutive data is transferred at one word per clock. The device must support burst mode.
Burst Copy-Back Option. When enabled, if a cache miss occurs, the chipset will initiate a second, burst cache line fill from main memory to the cache, the object being to maintain the status of the cache.
Preempt PCI Master Option. When enabled, PCI bus operations can be preempted by certain system operations, such as DRAM refresh, etc. Otherwise, they can take place concurrently.
IBC DEVSEL# Decoding. Allows you to set the type of decoding used by the ISA Bridge Controller (IBC) to determine which device to select. The longer the decoding cycle, the better chance the IBC has to correctly decode the commands. Choices are Fast, Medium and Slow (default).
Keyboard Controller Clock. Sets the speed of the keyboard controller (PCICLKI = PCI bus speed).
7.16 Mhz Default
PCICLKI/2 1/2 PCICLKI
PCICLKI/3 1/3 PCICLKI
PCICLKI/4 1/4 PCICLKI
CPU Pipeline Function. This allows the system controller to signal the CPU for a new memory address even before all data transfers for the current cycle are complete, resulting in increased throughput. Enabled means that address pipelining is active.
PCI Dynamic Decoding. When enabled, this setting allows the system to remember the PCI command which has just been requested. If subsequent commands fall within the same address space, the cycle will be automatically interpreted as a PCI command.
Master Retry Timer. This sets how long the CPU master will attempt a PCI cycle before the cycle is unmasked (terminated). The choices are measured in PCICLKs which the PCI timer. Values are 10 (default), 18, 34 or 66 PCICLKs.
PCI Pre-Snoop. Pre-snooping is a technique by which a PCI master can continue to burst to the local memory until a 4K page boundary is reached rather than just a line boundary.
CPU/PCI Write Phase. Determines the turnaround between the address and data phases of the CPU master to PCI slave writes. Choices are 1 LCLK (default) or 0 LCLK.
PCI Preempt Timer. This item sets the length of time before one PCI master preempts another when a service request has been pending.
Disabled No preemption (default).
260 LCLKs Preempt after 260 LCLKs
132 LCLKs Preempt after 132 LCLKs
68 LCLKs Preempt after 68 LCLKs
36 LCLKs Preempt after 36 LCLKs
20 LCLKs Preempt after 20 LCLKs
12 LCLKs Preempt after 12 LCLKs
5 LCLKs Preempt after 5 LCLKs
CPU to PCI POST/BURST. Data from the CPU to the PCI bus can be posted (buffered by the controller) and/or burst. This sets the methods.
POST/CON.BURST. Posting and bursting supported (default).

NONE/NONE. Neither supported.

POST/NONE. Posting but not bursting supported.

PCI CLK. Whether the PCI clock is tightly synchronized with the CPU clock, or is asynchronous. If your CPU, motherboard and PCI bus are running at multiple speeds of each other, e.g. Pentium 120, 60 MHz m/b and 30 MHz PCI bus, choose synchronise.
IRQ 15 Routing Selection. MISA=Multiplexed ISA for asynchronously interrupting the CPU. IRQ 15 is usually used for Secondary IDE channels or CD-ROMs.
CPU cycle cache hit same point. Working on this.
PCI cycle cache hit sam point. As above.
Arbiter timer timeout (PCI CLK) 2 x 32. Working on this.

Hard Disk Utility

Hard Disk Format

Will format your hard disk so it can receive new partitions.

IT WILL SMASH EVERYTHING ON YOUR HARD DISK!!! USE WITH CAUTION. A lot of inexperienced users have lost their sanity with this one. Several computer stores have made extra money with it! There's no need to do this unless you experience errors or if you want to change the interleave. DON'T TOUCH THIS IF YOU HAVE AN IDE DRIVE. It will perform a low level format and probably SCRAP your IDE hard drive. IDE is the standard drive type that nearly everyone has now. SCSI or ESDI drives shouldn't be low-level formatted. The new drives actually don't perform the low level format, but some old AT-Bus (IDE) drives you can scratch with this... This entry is only sensible for old MFM or RLL hard disks! Please refer to your hard disk manual to see how or if your hard disk can be low level formatted. Don't tell us we did not warn you.

Many manufacturers provide utilities to low level format their IDE drives (or any other types). Please refer to the comp.sys.ibm.pc.hardware.storage

FAQ for more technical information about this procedure. If normal (high level) hard disk formatting is required, you can use DOS FDISK to first erase and create partitions and then use FORMAT. It is also a good idea when you hard disk becomes inaccessible to see if it is just the system files that are corrupted. Most of the time, it is the case. SYS will do the job of replacing system files. Several packages (PC-Tools, Norton, etc.) provide utilities for repairing "damaged" HDD and FDD. Therefore, low level format is always of LAST RESORT when you encounter HDD problems.

Auto Detect Hard Disk

Handy when you "forgot" the specs of your hard drive. The BIOS will detect the number of cylinders, heads and sectors on your hard disk. In some BIOS versions, this option in the main SETUP menu.

Auto Interleave

Determines the optimum interleave factor for older hard disks. Some controllers are faster than others, and you don't want the sectors laid out so reading consecutive sectors usually results in just missing the sector you wanted and having to wait a whole disk rotation for it to come around again. On modern ones, it's always 1:1 (and even if it wasn't, you cannot reformat anyway).

Interleaving is specified in a ratio, n:1, for small positive integers n. Basically, it means that the next sector on the track is located n positions after the current sector. The idea is that data on a hard drive might spin past the heads faster than the adapter can feed it to the host. If it takes you more than a certain amount of time to read a sector, by the time you're ready for the next sector, the heads will have passed it already. If this is the case, the interleave is said to be "too tight". The converse, where the CPU spends more time than necessary waiting for the next sector to spin under the heads, is too "loose" of an interleave. Clearly, it is better to have too loose an interleave than too tight, but the proper interleave is better still. Especially since any controller with read-ahead cacheing can pull the whole track into its buffer, no matter how slow the CPU is about fetching the data down.

The 1:1 interleave arranges the sectors on a track as follows:

0 1 2 3 4 5 6 7 8 9 a b c d e f g (17-sectors, using base 17 for convenience, this is clearly the in-order arrangement, one after another)

This is 2:1 interleaving:

0 9 1 a 2 b 3 c 4 d 5 e 6 f 7 g 8

The CPU has a whole sector's worth of time to get the a sector's data taken care of before the next sector arrives. It shows which logical sector goes in each physical sector.

Anyway, an n:1 interleave restricts the transfer rate to 1/n the speed of a 1:1 interleave (which is better than 1 revolution per sector if the interleave is too tight!). No modern PC should require interleaving. Only MFM and RLL (maybe also ESDI) and floppy drives which are capable of it (you could format a 1.44 meg floppy to 21 sectors/track, which would require a 2:1 interleave to not exceed the 500 mbps speed of the controller...but why?).

Media Analysis

Scan the hard disk for bad blocks. It is performing a LOW LEVEL FORMAT on the track where bad sector is encountered to mark that sector as a bad. It could cause damage on user data, even if scanning itself is non-destructive (also on MFM, RLL disks). Therefore, DON'T USE this option to on AT-Bus (IDE), SCSI or ESDI drives. These drives store the bad block data themselves, so you don't have to tell them or scan the media! Recommendation: use a media analysis program provided by an utility package or your hard drive manufacturer.

Power Management
This menu appears on computers having the "Green PC" specification, an initiative of the EPA (Environmental Protection Agency of the United States) with its Energy Star program. The main purpose is to minimize power usage when the system stays inactive for a while. The standard is still not yet achieved among manufacturers, so expect to see several variations. On most cases, the power management strategies are incremental, meaning that the longer a system stays inactive, the more parts will close down.

There exists three power management schemes: APM (Advanced Power Management) proposed by Intel and Microsoft. ATA (AT Attachment) for IDE drives. DPMS (Display Power Management Signaling) matches video monitors and video cards so they may simultaneously shut down.

· Green Timer of Main Board: Allows to setup the time after which the CPU of an idle system will shut down. Disabled or a time interval ranging from 1 to 15 minutes are the usual options. 5 to 10 minutes recommended.

· Doze Timer: Amount of time before the system will reduce 80% of its activity.

· Standby Timer: Amount of time before the system will reduce 92% of its activity.

· Suspend Timer: Amount of time after the system goes in the most inactive state possible, which is 99%. After this state, the system will require a warm up period so the CPU, hard disk and monitor may go online.

· HDD Standby Timer: Allows to setup the time after which the hard disk of an HHD idle system (no HDD access) will shut down. A terrific option if you have a somewhat noisy hard drive unit. The choice of a time interval depends on how hard disk intensive is your operating system. This may depends also on the amount of memory available. You should setup a longer time interval, like 10 minutes, if you only have 8MB of RAM and running OS/2 or Windows. For a plain/standard DOS environments, 2 to 5 minutes are recommended. If you have a comfortable 16 MB or more, the time lapse can be shorter. There are some reports that this option may cause problems with slave hard drives (AMI BIOS only?).

Frequently Asked Questions

How do I clear the BIOS memory?

Three alternatives are available depending of your type of motherboard:

· Enter BIOS Setup and change to settings to Power-On Defaults.

· Disconnect the battery.

· Insert appropriate jumper an wait until the BIOS memory is cleared (see mainboard documentation, the jumper is often located near the battery).

Sometimes this is possible with DIP switches on the motherboard. Sometimes (if not), you will have to remove the battery. And sometimes (if no DIP's and no removable battery, and not willing to desolder the battery), you can short the battery with a resistor to lower the current available for the CMOS.

This is only recommendable as a very last option. The NiCad cells often employed have a very low internal resistance, so the resistor will have to be of a very low value for the voltage to drop significantly. The corresponding current would be quite high, which is not very good for battery life. A better option would be to use a resistor to discharge the battery. Obviously, this only makes sense when you have a NiCad cell (which will be recharged every time you turn the computer on) as opposed to a lithium cell (which cannot be recharged). In the former case, a resistor of 39 Ohm will discharge the battery in under half an hour relatively safely.

Another good way to discharge the NiCad is to put a 6 volt lantern lamp across it, and let it discharge completely. Not only does it provide an effective load, it also gives a visual indication of the charge state. It's a good way to prevent "ghost memory" that's so common to NiCads. Metal Nickel Hydride batteries are now being seen in some systems. They don't have this problem and they are more $$.

Can I upgrade my BIOS?

Most BIOSes are specifically designed for a motherboard and its chipset. Therefore, on rare occasions you can upgrade your BIOS for a newer version. It is often less troublesome to buy a new motherboard that comes with its own BIOS and transfer your CPU (memory, cache memory and adaptor cards...) than start hunting around for a new BIOS chip. I know very few computer stores who sell BIOS chips separately. However, it is possible to upgrade your BIOS so it may support new hardware. By browsing in computer magazines (like Computer Shopper, PC Magazine, etc.) you will find adds on companies that specialize on that sort of thing. The information they need is the Serial Number for the BIOS chip. It is the long number that prints out when you boot up. It includes the BIOS date, the chipset, etc. The price tag can vary greatly (from $10 to $80), so are the BIOS upgrades offered. (Does anyone have supplementary information on this, like good-bad experiences with BIOS upgrade? I already had 2 feedback on this, and they all agree it is a little tricky, but it works).