Contact debounce and
digital faultfinding in sequential circuits.

The clock signal to counters and shift registers must be a clean square wave, or these circuits become in effect random number generators. Unless it has its contacts debounced, a common or garden switch will not do. The circuit to do that is very simple if the approximate period of the bounce is known, but the following configuration will work at all times:

The Muller C- element has a gate version: There is not much to say about the circuit. The storage element's outputs persist in the absence of input pulses, because the gates enforce each other's state through positive feedback. Additional input pulses to the same input are ignored.

The circuit does not look impressive, but what you can do with it certainly is: It can generate the master clock signal for a sequential digital circuit. The cycle time can then last for minutes, rather than nanoseconds (provided there are no dynamic registers involved). You can then monitor the logic levels on nodes of interest at your leasure. Most simple microcontrollers only need 7 cycles to execute their longest commands.

In these days, integrated digital simulator and autorouter pakages are quite common, so there shouldn't be errors lurking in a design by the time it gets to the prototype board stage. There is still going to be some need for some old fashioned on- board digital troubleshooting, though, because of:



This is well for logic faults, and some timing faults, but what about timing faults which are only manifested near the maximum operational frequency? You can increase the frequency until an error is met. Then the Muller C- element is augmented by a monostable. Next, all low parts of the cycles can be tested in one go, all the high parts in another go. The cycle (and part of this cycle) which causes the trouble can be detected, by comparing expected and actual logic levels.

If you are lucky, maybe some storage element is latching data too soon, or too late. Good designs are unlikely to suffer from that, though. More likely, it will be a matter of the previous stage, which supplies the data, not being fast enough. It will have to be rebuilt using a faster technology, or by exploiting increased parallelism.

Some digital faultfinding can be thought to require a $10,000 digital storage oscilloscope or logic analyser. It looks as though part of this work can be done for next to nothing.

In the future, the site will present more digital faultfinding circuits: A pulse injector and pulse detector pair, in particular, is one way of verifying that a gate is functional, without momentarily disconnecting it from the previous stages.

Last month's section: Rectified sinewave spectrum 1