1. Review
and Introduction
1.1. O/S
Code Structure
-
1.2. XINU
Code Structure
-
1.3. Application
View of the O/S
- 2. Processes
- Introduction
-
2.1. XINU
Process Creation Primitives
-
2.2. Stacks
and Processes
-
2.3. Introduction
to XINU Process Synchronization
- 3. Process
Memory Organization
-
3.1. Contents
of the Execution Stack
- 4. Talking
to Devices - An Introduction to Busses
-
4.1. The
PDP-11 Bus
-
4.2. Bus
Architecture for the PC
- 5. Hardware
Interrupt Generation and Acknowledgement
-
5.1. Hardware
Interrupt Generation and Acknowledgement - Part 2
-
5.2. Hardware
Interrupt Generation and Acknowledgement - Points Raised
- 6.
Exceptions
and Traps
- 7.
Polled
I/O
- 8. Issuing
Commands to Devices - Introduction
-
8.1. Memory-Mapped
Control
-
8.2. Control
via Special Instructions
-
8.3. Transferring
Data To and From Devices - Introduction
-
8.4. Talking
to Devices - Summary and Review
- 9. Device
Examples - Introduction
- 9.1. Serial
Line Unit Example
-
9.1.1. Sending
a Character
-
9.1.2. Receiving
a Character
- 9.2. Disk
Device - Overview
-
9.2.1. Making
a Request of a Disk
- 10. List
Processing in Xinu
-
10.1. Layout
of XINU Lists
-
10.2. Storage
Management for XINU Lists
-
10.3. List
Manipulation Routines in XINU
- 11. Scheduling
and Context Switching in XINU - Introduction
-
11.1. The
XINU PCB
-
11.2. Selecting
the Next Ready Process
-
11.3. The
NULL Process
-
11.4. The
Resched and Ready Routines
- 12. Process
Management in XINU - Introduction
-
12.1. System
Call Basics
-
12.2. System
Calls in XINU - overview
-
12.3. Process
Management System Calls in XINU
- 13. Process
Coordination in XINU - Introduction
- 13.1. Synchronization
Within The Kernel - Introduction
-
13.1.1. Disabling
Interrupts
-
13.1.2. Test
and Set
-
13.2. Application
Synchronization Via Semaphores
- 14. Message
Passing - Introduction
-
14.1. Message
Passing in General
-
14.2. Message
Passing Routines - Semantics
-
14.3. Message
Passing Routines - Implementation
- 15. Memory
Management - Introduction
-
15.1. Memory
Allocation Routines
- 15.2. Implementation
- Overview
-
15.2.1. Heap
Storage
-
15.2.2. Stack
Storage
- 16. Low
Level Interrupt Processing - Introduction
-
16.1. The
Two Halves in XINU Interupt Processing
-
16.2. The
Low-Level Interrupt Routines in XINU
-
16.3. Knowing
the Source of the Interrupt
-
16.4. Final
Words about ISRs
- 17. XINU
Clock Management - Introduction
-
17.1. Clock
Hardware
-
17.2. Slowing
the Clock
-
17.3. Putting
Processes to Sleep
-
17.4. Deferring
Clock Processing
-
17.5. The
Clock ISR
- 18. TTY
Driver - Introduction and Organization
-
18.1. Upper
and Lower Half Interaction
- 18.2. TTY
Control Block
-
18.2.1. TTY
Control Routine
-
18.3. Upper
Half Routines
-
18.4. Lower
Half Output Processing
-
18.5. Lower
Half Input Processing
- 19. XINU
File System - Introduction
- 19.1. File
Organization
-
19.1.1. Directory
Entry Contents
-
19.1.2. Index
Blocks
-
19.1.3. Data
Blocks
-
19.2. Operations
on Index Blocks
-
19.3. File
I/O Routines
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