Po-Hung Chen (David)
http://www.geocities.com/SiliconValley/Haven/5528
EDUCATION: Bachelor of Science, Electrical Engineering
University of California, Davis, June 1999
WORKING Design Engineer (September 99 - March 2000)
EXPERIENCE:
Alcor Micro Inc., Santa Clara, California
Completed an existed USB host model test bench: involved in tracing
signals and inserting proper delay time. Completed VHDL and test bench file for an existed ICC model.
Inserted a vendor Timer mode and adjusted on the USB host and ICC models.
Enhanced the USB host model in VHDL by adding on an auto-repeat-naking feature.
Tested the design on FPGA chip in the real time and under various
applications.
Designed PS/2 I/O interface for a USB keyboard. Captured and interpreted
the PS/2 & USB Bus activities/data packet format. Designed the
block/state diagram for it and implemented/coded in VHDL.
ASIC Design Engineer ( May 2000 to present)
Chip Express Inc., Santa Clara, California
Performed layout, and pre/post-layout static timing analysis/simulation
on many customers designs from their synthsized netlists. Produced back
annotation data and generated mask data for the design to Fab.
Interacted with customers and FAEs in reporting and solving problems.
Documented the flow and specification/Q&A of each step.
SCHOOL VHDL Design
PROJECT: Designed projects with VHDL, simulated using Synopsys? class library and design analyzer, synthesized using Xilinx?s library and design manager. Tested and downloaded on Xilinx FPGA XC4005E-3-PC84 board. These projects included 1) an 8 bit shift register 2) an elevator controller by modeling finite state machines. 3) an 8 bit ALU and register file. 4) a processor with an 8-bit address bus and 8-bit bi-directional data bus for accessing both instructions & data.
Logic Design
Used Altera Maxplus II, truth table, K-map, MSI and PAL Devices to design MUX and combinational logic network. Designed a ALU and Data path, a sequential circuit by state diagram, and 4-bit CPU by using Maxplus II to design and simulate including looking through the schematics and waveforms.
Digital IC Design
Determined the VTC of enhancement load, resistive load NMOS, and CMOS inverter. Built a dynamic and a static D flip-flop from inverters and transistors. Designed a full adder using a standard 2
PMOS Building
Applied oxidation, photolithography, impurity diffusion, metallization, etching to produce polySi-gate pMOS test chip.
Analog Circuit Design
Designed and verified logic gates? operation in standard logic families. Designed Single-Transistor Amplifier.
RELATED Digital Systems I&II Signals & System I &II Device Physics I&II
COURSES: Digital IC Control Systems IC Fabrication
Electromagnetism Analog Circuit
SKILLS: Operating Systems: MS-DOS, UNIX Workstations, Apple MacOSm PC Windows 3.x, Windows 95/98/2000
Programming Languages: VHDL, JAVA 1.2, JavaScript, C, C-shell/script, PASCAL,
Assembly Language in SAL, MAL, and TAL, MIPS RISC machine language, HTML
Tools: Adobe Photoshop, Adobe Acrobat Reader, MS Word/Excel/PowerPoint, H-SPICE, Matlab, Altera Maxplus II, Synopsis, Oscilloscope, Logic Analyzer, CATC View, USB View/Check, ModelSim, Vslick, Cadence Qplace, Verilog simulator, Synopsis Prime Time & dc-shell, xemacs, Lotus notes.
NJStar 4.2, E-trade, SPICE, Matlab, Altera Maxplus II, Espresso, Synopsis
Internet: Netscape, Mosaic, FTP, Turbogopher, Juno, Pine, Eudora, ICQ
Foreign Language: Fluent in Mandarin
ACTIVITIES: Bible Study Leader, College English Fellowship, Davis (9/96-6/99)
Sunday School song leader, Christian Assembly of Cupertino (7/93-9/95)
Member, IEEE (10/98-Present)
REFERENCES: Available upon request